公开(公告)号：US10114920B1

公开(公告)日：2018-10-30

申请号：US15197142

申请日：2016-06-29

申请人： CADENCE DESIGN SYSTEMS, INC.

发明人： Umesh Gupta ,  Shashank Tripathi ,  Naresh Kumar ,  Arvind Nembili Veeravalli ,  Prashant Sethia ,  Ritika Govila

IPC分类号： G06F17/50

摘要： A netlist of a multiple voltage circuit design having a plurality of power domains is established, then inter-power domain (IPD) paths traversing the circuit design are identified, according to whether they traverse multi-supply elements, or are clock paths capturing such a path. The netlist is then pruned to disable or remove cells or stages not traversed by an IPD path. A timing analyzer conducts a multi-domain timing analysis of the IPD timing paths in the pruned IPD netlist. Thereby, the circuit design is thoroughly tested according to the applicable ranges of voltage conditions without excessive runtime.

公开(公告)号：US10915685B1

公开(公告)日：2021-02-09

申请号：US16222638

申请日：2018-12-17

申请人： Cadence Design Systems, Inc.

发明人： Umesh Gupta ,  Naresh Kumar ,  Rakesh Agarwal ,  Sukriti Khanna ,  Jayant Sharma ,  Ritika Govila

IPC分类号： G06F17/50 ,  G06F30/3312 ,  G06F30/327 ,  G06F30/394 ,  G06F111/04 ,  G06F111/20 ,  G06F119/12

摘要： The present embodiments relate to static timing analysis (STA) of circuits. The STA can include determining graph based analysis (GBA) delays of timing paths within the circuit. Path based analysis (PBA) delays of a subset of timing paths can be determined to generate circuit stage credit values for circuit stages in the circuit. The circuit stage credit values can be used to adjust GBA delays of the timing paths. Prediction functions can be utilized to predict or estimate PBA delays of timing paths thereby avoiding the determination of actual PBA delays of the timing paths.

公开(公告)号：US10776547B1

公开(公告)日：2020-09-15

申请号：US16600927

申请日：2019-10-14

申请人： Cadence Design Systems, Inc.

发明人： Umesh Gupta ,  Naresh Kumar ,  Prashant Sethia ,  Ritika Govila ,  Jayant Sharma

IPC分类号： G06F30/3312 ,  G06F16/901 ,  G06F119/12

摘要： A static timing analysis system for finding timing violations in a digital circuit design prior to circuit fabrication, and associated methods, use infinite-depth path-based analysis (IPBA) to achieve reduced pessimism as opposed to systems or methods employing only graph-based analysis (GBA), but with greatly reduced compute time requirements, or greater logic path coverage, versus systems or methods employing conventional or exhaustive path-based analysis. IPBA achieves the improved coverage or compute time results by slotting nodes of a circuit design graph into stages, propagating phases stage-by-stage for all paths in parallel, and merging phases wherever possible during the analysis.