公开(公告)号：US11275882B1

公开(公告)日：2022-03-15

申请号：US16523112

申请日：2019-07-26

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Elias Lee Fallon ,  Regis R. Colwell ,  Hua Luo ,  Namita Bhushan Rane

IPC: G06F30/398 ,  G06K9/62 ,  G06N20/00

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design schematic and an electronic design layout and analyzing, via machine learning, at least one schematic feature from a pair of devices associated with the electronic design schematic. Embodiments may further include determining, based, at least in part, upon the analyzing, whether the pair of devices should be grouped together.

公开(公告)号：US11263381B1

公开(公告)日：2022-03-01

申请号：US17193357

申请日：2021-03-05

Applicant: Cadence Design Systems, Inc.

Inventor： Randall Scott Lawson ,  Regis R. Colwell ,  Richard Allen Woodward, Jr. ,  Rahil Rajesh Kothari ,  Mahmoodreza Jahanseirroodsari

IPC: G06F30/398 ,  G06F30/12 ,  G06F113/18

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using a processor, an electronic design and providing, at a graphical user interface, an option to change an object associated with the electronic design. Embodiments may further include identifying a damage area associated with the electronic design, the damage area including an object therein. Embodiments may also include generating a polygon for the damage area and caching one or more voids located outside of the damage area. Embodiments may further include performing a cut and stamp operation on a portion of the electronic design associated with the damage area and populating, at the graphical user interface, a repaired damage area.

公开(公告)号：US11087060B1

公开(公告)日：2021-08-10

申请号：US16524859

申请日：2019-07-29

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Elias Lee Fallon ,  Regis R. Colwell ,  Hua Luo ,  Namita Bhushan Rane ,  Sheng Qian

IPC: G06F30/39 ,  G06N20/00

Abstract: The present disclosure relates to a computer-implemented method for electronic design. Embodiments may include receiving, using at least one processor, an electronic design schematic and an electronic design layout and training a model using at least one predictor associated with the electronic design layout. Embodiments may further include obtaining an updated model, based upon, at least in part, the training. Embodiments may also include applying the updated model to a second electronic design schematic or a second electronic design layout, wherein one or more hard constraints or one or more soft constraints or both are created, based upon, at least in part, the model.

公开(公告)号：US10949596B1

公开(公告)日：2021-03-16

申请号：US16742266

申请日：2020-01-14

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hua Luo ,  Regis R. Colwell ,  Qian Xu

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/31 ,  G06N3/12 ,  G06F7/22 ,  G06F111/02

Abstract: Embodiments may include receiving an unplaced layout associated with an electronic circuit design and one or more grouping requirements. Embodiments may further include identifying instances that need to be placed at the unplaced layout and areas of the unplaced layout configured to receive the instances. Embodiments may also analyzing one or more instances that need to be placed at the unplaced layout and the one or more areas of the unplaced layout configured to receive the one or more instances. Embodiments may further include determining a location and an orientation for each of the one or more instances based upon, at least in part, the analyzing. Embodiments may also include generating a placed layout based upon, at least in part, the determined location and orientation for each of the one or more instances. Embodiments may further include during the generation of the placed layout, routing the placed layout.

公开(公告)号：US10747936B1

公开(公告)日：2020-08-18

申请号：US16527412

申请日：2019-07-31

Applicant: Cadence Design Systems, Inc.

Inventor： Hua Luo ,  Regis R. Colwell ,  Wangyang Zhang

IPC: G06F30/394 ,  G06N3/12

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having one or more unoptimized nets. Embodiments may further include applying a genetic algorithm to the electronic design, wherein the genetic algorithm includes a two stage routing analysis, wherein a first stage analysis is an intra-row routing analysis and a second stage is an inter-row routing analysis. Embodiments may also include generating an optimized routing of the one or more nets and displaying the optimized routing at a graphical user interface.