公开(公告)号：US11842130B1

公开(公告)日：2023-12-12

申请号：US17503001

申请日：2021-10-15

Applicant: Cadence Design Systems, Inc.

Inventor： Saleha Khatun ,  David Varghese ,  Roland Ruehl

IPC: G06F30/27 ,  G06F30/367

CPC classification number: G06F30/27 ,  G06F30/367

Abstract: Various embodiments provide for predicting a simulation result for a circuit design using a machine learning model, which can be used as part of a process of an electronic design automation (EDA) system that measures a circuit design (e.g., timing, power, voltage, current, etc.). In particular, various embodiments described herein can enable modeling simulated time measurements of a circuit design, and can enable such modeling with minimal usage of simulation result data.

公开(公告)号：US11003825B1

公开(公告)日：2021-05-11

申请号：US16583643

申请日：2019-09-26

Applicant: Cadence Design Systems, Inc.

Inventor： Saleha Khatun ,  Sheng Qian ,  Wangyang Zhang ,  Elias Lee Fallon

IPC: G06F30/30 ,  G06F30/38 ,  G06F30/392 ,  G06F30/398 ,  G06F111/06

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design and determining an objective function associated with the electronic design. Embodiments may further include optimizing the objective function using Bayesian optimization and generating a best hyper-parameter setting based upon, at least in part, the Bayesian optimization.