公开(公告)号：US10783300B1

公开(公告)日：2020-09-22

申请号：US16218678

申请日：2018-12-13

Applicant: Cadence Design Systems, Inc.

Inventor： Sushobhit Singh ,  Naresh Kumar ,  Beenish ,  Ankur Gulati ,  Vishal Karda ,  Shashank Prasad

IPC: G06F30/3312 ,  G06F30/33 ,  G06F30/3315 ,  G06F119/12

Abstract: The present disclosure relates to a system for performing static timing analysis in an electronic design. Embodiments may include providing, using at least one processor, an electronic design and extracting hierarchical crossing path exception information from a hierarchical design view associated with the electronic design. Embodiments may further include transferring the hierarchical crossing path exception information to a block view associated with the electronic design and extracting a timing model based upon, at least in part, the hierarchical crossing path exception information. Embodiments may also include implementing the timing model at a top-level view associated with the electronic design.