Patent search ap:("Cadence Design Systems Page Inc.") AND inv:"Beenish"

1.

发明授权
Systems and methods for extracting hierarchical path exception timing models 有权

公开(公告)号：US10783300B1

公开(公告)日：2020-09-22

申请号：US16218678

申请日：2018-12-13

Applicant: Cadence Design Systems, Inc.

Inventor： Sushobhit Singh , Naresh Kumar , Beenish , Ankur Gulati , Vishal Karda , Shashank Prasad

IPC: G06F30/3312 , G06F30/33 , G06F30/3315 , G06F119/12

Abstract: The present disclosure relates to a system for performing static timing analysis in an electronic design. Embodiments may include providing, using at least one processor, an electronic design and extracting hierarchical crossing path exception information from a hierarchical design view associated with the electronic design. Embodiments may further include transferring the hierarchical crossing path exception information to a block view associated with the electronic design and extracting a timing model based upon, at least in part, the hierarchical crossing path exception information. Embodiments may also include implementing the timing model at a top-level view associated with the electronic design.

2.

发明授权
System and method for performing sign-off timing analysis of electronic circuit designs 有权

公开(公告)号：US11455450B1

公开(公告)日：2022-09-27

申请号：US17337937

申请日：2021-06-03

Applicant: Cadence Design Systems, Inc.

Inventor： Sushobhit Singh , Arvind Nembili Veeravalli , Naresh Kumar , Beenish , Mahesh Diwakar Sadhankar , Ankit Sethi

IPC: G06F30/30 , G06F30/3315 , G06F30/31 , G06F119/06 , G06F119/12 , G06F111/02

Abstract: Embodiments include herein are directed towards a method for dynamic voltage and frequency scaling (DVFS) based timing signoff associated with an electronic design environment. Embodiments may include receiving, using a processor, an electronic design and specifying, via a graphical user interface, a voltage sweep for each power net associated with the electronic design. Embodiments may further include specifying, via the graphical user interface, at least one voltage sweep to be excluded from analysis. Embodiments may also include automatically generating DVFS configurations based upon, at least in part, the voltage sweep for each power net and the at least one voltage sweep to be excluded from analysis.

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