公开(公告)号：US09159423B1

公开(公告)日：2015-10-13

申请号：US13631171

申请日：2012-09-28

Applicant: Cadence Design Systems, Inc.

Inventor： Sandeep Brahmadathan ,  Srinivas Suresh Revankar

IPC: G11C16/06 ,  G11C16/04

CPC classification number: G11C16/04 ,  G06F11/1068 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10

Abstract: The present invention provides a method and system to reduce the impact of errors introduced in flash devices while providing improved system performance through optimized activities with limited impact to overhead using a predetermined threshold value or threshold device value. In an embodiment, a device threshold value is compared with the cumulative number of data bits having a zero value of a target page and an error type of the target page is assessed to determine whether the target page is available to be written to. Therefore for a highly effective method for is provided for determining the availability of a page, having a block address and page address, to be identified, in one instance, as being an erased page that is available to be written to.

Abstract translation: 本发明提供一种减少闪存装置中引入的误差的影响的方法和系统，同时通过使用预定的阈值或阈值装置值对开销的有限影响的优化活动提供改进的系统性能。 在一个实施例中，将设备阈值与具有目标页面的零值的数据位的累积数量进行比较，并且评估目标页面的错误类型以确定目标页面是否可用于被写入。 因此，提供了一种用于确定具有要被识别的块地址和页面地址的页面的可用性的高效方法，在一个实例中，作为可被写入的擦除页面。