公开(公告)号：US10990733B1

公开(公告)日：2021-04-27

申请号：US16814928

申请日：2020-03-10

Applicant: Cadence Design Systems, Inc.

Inventor： Vibhor Garg ,  Amit Dhuria

IPC: G06F30/3315 ,  G06F119/12

Abstract: According to certain aspects, the present embodiments include techniques for performing a single timing analysis run for a plurality of views representing different modes and/or corners. An embodiment analyzes and maintains relevant timing information that is different for different views, but otherwise maintains the same information for all views. This allows each individual view in a single run to be analyzed in the same manner as separate runs for each separate view, thereby ensuring the same QoR. These and other embodiments provide substantial savings in runtime and memory consumption over other approaches.

公开(公告)号：US11144698B1

公开(公告)日：2021-10-12

申请号：US16946677

申请日：2020-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Vibhor Garg ,  Edward J. Martinage ,  Amit Dhuria ,  Krishna Prasad Belkhale

IPC: G06F30/392 ,  G06F30/396 ,  G06F30/31 ,  G06F30/327 ,  G06F111/12

Abstract: An approach is described for a method, system, and product, that includes identification/generation of a synthesized netlist for use in optimization and placement, generation and utilization of multiple uncertainty values for an early clock tree for guiding optimization and placed of circuit elements in a placeopt process that operates on a path by path basis. In some embodiments, the approach further comprises execution of clock tree synthesis, and routing the synthesized clock tree. In some embodiments, uncertainty values are propagated along data paths where each data path is associated with an uncertainty value, and where each path is optimized and placed on a path my path basis in order to meeting timing requirements and one or more design goals.

公开(公告)号：US10467365B1

公开(公告)日：2019-11-05

申请号：US15483307

申请日：2017-04-10

Applicant: Cadence Design Systems, Inc.

Inventor： Pawan Kulshreshtha ,  Vibhor Garg

IPC: G06F17/50

Abstract: The present disclosure relates to a system for use in electronic circuit design. The system may include a computing device configured to receive, using at least one processor, an electronic design. The at least one processor may be further configured to generate a common path pessimism removal (“cppr”) database configured to store one or more cppr tags obtained from an initial timing analysis of at least a portion of the electronic design. The at least one processor may be further configured to apply the one or more cppr tags during a block-level timing analysis.

公开(公告)号：US08745561B1

公开(公告)日：2014-06-03

申请号：US13957373

申请日：2013-08-01

Applicant: Cadence Design Systems, Inc.

Inventor： Vibhor Garg ,  Krishna Belkhale ,  Pawan Kulshreshtha ,  Hakan Yalcin

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5031 ,  G06F2217/84

Abstract: A system and method are provided for common path pessimism removal or reduction (CPPR) in a timing database provided to guide transformative physical optimization/correction of a circuit design for an IC product to remedy operational timing violations detected in the circuit design. Pessimism is reduced through generation of a common path pessimism removal (CPPR) tree structure of branching nodes, and operational timing characteristics of each node. The CPPR tree structure is used to avoid exponential phases propagating in an exploratory manner through the system design, as well as the resultant memory footprint thereof. Additionally, back-tracing node-by-node through the circuit design for each and every launch and capture flip flop pair end point through each possible path thereof is avoided.

Abstract translation: 提供了一种系统和方法，用于在定时数据库中提供通用路径悲观消除或减少（CPPR），以指导用于IC产品的电路设计的变换物理优化/校正，以补救在电路设计中检测到的操作定时违规。 悲观主义通过生成分支节点的公共路径悲观消除（CPPR）树结构以及每个节点的运行时序特征来减少。 CPPR树结构用于避免通过系统设计以探索性方式传播的指数相位以及其产生的内存占用。 另外，避免了通过电路设计的每个启动和捕捉触发器对端点通过其每个可能的路径逐个跟踪节点。