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    System and method for common path pessimism reduction in timing analysis to guide remedial transformations of a circuit design
    1.
    发明授权
    System and method for common path pessimism reduction in timing analysis to guide remedial transformations of a circuit design 有权
    用于通用路径悲观的系统和方法减少时序分析，以指导电路设计的补救转换

    公开(公告)号：US08745561B1

    公开(公告)日：2014-06-03

    申请号：US13957373

    申请日：2013-08-01

    Applicant: Cadence Design Systems, Inc.

    Inventor： Vibhor Garg ,  Krishna Belkhale ,  Pawan Kulshreshtha ,  Hakan Yalcin

    IPC: G06F17/50

    CPC classification number: G06F17/50 ,  G06F17/5031 ,  G06F2217/84

    Abstract: A system and method are provided for common path pessimism removal or reduction (CPPR) in a timing database provided to guide transformative physical optimization/correction of a circuit design for an IC product to remedy operational timing violations detected in the circuit design. Pessimism is reduced through generation of a common path pessimism removal (CPPR) tree structure of branching nodes, and operational timing characteristics of each node. The CPPR tree structure is used to avoid exponential phases propagating in an exploratory manner through the system design, as well as the resultant memory footprint thereof. Additionally, back-tracing node-by-node through the circuit design for each and every launch and capture flip flop pair end point through each possible path thereof is avoided.

    Abstract translation: 提供了一种系统和方法，用于在定时数据库中提供通用路径悲观消除或减少（CPPR），以指导用于IC产品的电路设计的变换物理优化/校正，以补救在电路设计中检测到的操作定时违规。 悲观主义通过生成分支节点的公共路径悲观消除（CPPR）树结构以及每个节点的运行时序特征来减少。 CPPR树结构用于避免通过系统设计以探索性方式传播的指数相位以及其产生的内存占用。 另外，避免了通过电路设计的每个启动和捕捉触发器对端点通过其每个可能的路径逐个跟踪节点。

    System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design
    2.
    发明授权
    System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design 有权
    指导由物理实施数据定义的电路设计的补救变换的系统和方法，以减少电路设计中检测到的定时违规所需的物理校正

    公开(公告)号：US08788995B1

    公开(公告)日：2014-07-22

    申请号：US13842178

    申请日：2013-03-15

    Applicant: Cadence Design Systems, Inc.

    Inventor： Naresh Kumar ,  Prashant Sethia ,  Amit Dhuria ,  Krishna Belkhale

    IPC: G06F17/50

    CPC classification number: G06F17/50 ,  G06F17/5031 ,  G06F17/5081 ,  G06F2217/84

    Abstract: A system and method are provided for pessimism reduction of a timing database provided for optimization of a circuit design. Pessimism is reduced through generation of a hybrid graph-based static timing analysis (GBA) and path-based static timing analysis (PBA STA) database. PBA is selectively performed on the most critical GBA identified timing violations with the goal of reducing erroneous pessimism in operational timing characteristics passed on to the physical implementation corrective optimizer module to thereby reduce unnecessary fixing and transformations upon the circuit design to correspondingly reduce design time, temporary storage space, needed processing power for timing closure and to result in a finished operable and tangible circuit device with reduced area, power requirements, and decreased cost.

    Abstract translation: 提供了一种系统和方法，用于减少为电路设计的优化提供的定时数据库的悲观情绪。 通过生成基于混合图的静态时序分析（GBA）和基于路径的静态时序分析（PBA STA）数据库来减少悲观。 选择性地对最关键的GBA识别的定时违规执行PBA，目的是减少传递到物理实现校正优化器模块的操作时序特性的错误悲观，从而减少电路设计上的不必要的固定和转换，从而相应地减少设计时间 存储空间，所需的处理能力用于定时关闭，并且导致完成的可操作和有形的电路装置，其面积减小，功率要求低，成本降低。

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