公开(公告)号：US11347914B1

公开(公告)日：2022-05-31

申请号：US17337984

申请日：2021-06-03

申请人： Cadence Design Systems, Inc.

发明人： Wei-Cheng Chen ,  Yuan-Kai Pei ,  Yu-Chi Su

IPC分类号： G06F30/31 ,  G06F30/36 ,  G06F119/06 ,  G06F111/02

摘要： The present disclosure relates to a method for use with an electronic design. Embodiments may include performing, using a processor, an electronic design process on a portion of an electronic design. Embodiments may also include automatically monitoring the electronic design process on a periodic basis using a pulse monitor to acquire one or more sampling results and storing the one or more sampling results. Embodiments may further include providing, during the electronic design process, the one or more sampling results to a graphical user interface.

公开(公告)号：US08910100B1

公开(公告)日：2014-12-09

申请号：US14337880

申请日：2014-07-22

申请人： Cadence Design Systems, Inc.

发明人： Thomas Wilson ,  Arnold Ginetti ,  Kenneth Ferguson ,  Yuan-Kai Pei

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5072

摘要： The subject system and method are generally directed to the user-friendly insertion of at least one device, and optionally chains of devices, into at least one pre-existing chain of interconnected devices within a graphical representation of a circuit design such as a circuit layout, circuit mask, or a schematic. The system and method provide for discerning the intended insertion points and performing remedial transformations of the devices within the chains to ensure compliance with both structural and operational requirements of the circuit design.

摘要翻译： 主题系统和方法通常涉及在电路设计的图形表示（例如电路布局）内将至少一个设备和可选的设备链的用户友好插入到互连设备的至少一个预先存在的链中 ，电路掩模或示意图。 该系统和方法提供了识别预期插入点并执行链内设备的补救变换，以确保符合电路设计的结构和操作要求。

公开(公告)号：US10922469B1

公开(公告)日：2021-02-16

申请号：US16917080

申请日：2020-06-30

申请人： CADENCE DESIGN SYSTEMS, INC.

发明人： Yuan-Kai Pei ,  Gautam Kumar ,  Gerard Tarroux

IPC分类号： G06F30/392 ,  G06F30/31 ,  G06F111/20 ,  G06F111/02

摘要： Embodiments described herein provide a new layout editor tool allowing designers to concurrently edit various aspects of an electronic circuit layout, even at disparate hierarchical levels of the design. The new layout editor tool enables multiple electronic circuit designers to concurrently edit a layout a different hierarchical levels, by logically establishing editable child sub cell-level partitions within a parent layout-level partition, each of which representing various components of the same electronic circuit layout.

公开(公告)号：US09779193B1

公开(公告)日：2017-10-03

申请号：US14675665

申请日：2015-03-31

申请人： Cadence Design Systems, Inc.

发明人： Arnold Ginetti ,  Yuan-Kai Pei ,  Yu-Chi Su

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/74

摘要： Disclosed are techniques for implementing electronic design layouts with symbolic representations. These techniques determine an abstraction scope of a layout circuit component in a layout of an electronic design by referencing a user input or one or more default settings of the abstraction mechanism and identify first data that are included in or associated with a schematic symbol for the layout circuit component by traversing data from a symbolic representation data source with reference to the abstraction scope with the layout editing mechanism. In addition, these techniques further generate a symbolic representation for the layout circuit component by reproducing at least some of the first data in the layout and perform one or more layout operations on the symbolic representation to improve the layout and to generate a result set for the one or more layout operations.