公开(公告)号：US06611857B1

公开(公告)日：2003-08-26

申请号：US09713583

申请日：2000-11-15

申请人： Carl E. Lemonds ,  Alan Gatherer

发明人： Carl E. Lemonds ,  Alan Gatherer

IPC分类号： G06F752

CPC分类号： G06F7/5318 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/3287 ,  G06F7/5338 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171

摘要： A multiplier (12) is disclosed that includes an encoder (36), a hierarchy of compressors (40, 42, 44, 50, 52, 60 and 70), a bit detector (130) and a switch (134). The encoder (36) is operable to receive a first and second encoder input. The compressors (40, 42, 44, 50, 52, 60 and 70) are coupled to the encoder (36). The compressors (40,42, 44, 50, 52, 60 and 70) are operable to receive a first number of inputs and to generate a second number of outputs, with the second number being less than the first number. The bit detector (130) is operable to monitor the first encoder input to determine whether the first encoder input is in a reduced precision range (28). The bit detector (130) is also operable to deactivate a subset of the compressors (40 and 50) when the bit detector (130) determines that the first encoder input is in the reduced precision range (28). The switch (134) is coupled to a specified one of the compressors (42). The switch (134) is operable to redirect the path of one of the outputs for the specified compressor (42) such that the subset of the compressors (40 and 50) is removed from the path when the bit detector (130) determines that the first encoder input is in the reduced precision range (28).

摘要翻译： 公开了一种乘法器（12），其包括编码器（36），压缩机层级（40,42,44,50,52,60和70），位检测器（130）和开关（134）。 编码器（36）可操作以接收第一和第二编码器输入。 压缩机（40,42,44,50,52,60和70）联接到编码器（36）。 压缩机（40,42,44,50,52,60和70）可操作以接收第一数量的输入并产生第二数量的输出，其中第二数量小于第一数量。 位检测器（130）可操作以监视第一编码器输入以确定第一编码器输入是否处于减小的精度范围（28）。 当位检测器（130）确定第一编码器输入处于降低的精度范围（28）时，位检测器（130）还可操作以停用压缩机（40和50）的子集。 开关（134）耦合到指定的一个压缩机（42）。 开关（134）可操作以重定向用于指定的压缩机（42）的输出之一的路径，使得当位检测器（130）确定压缩机（40）和（50）的子集 第一个编码器输入处于减小的精度范围（28）。

公开(公告)号：US5889691A

公开(公告)日：1999-03-30

申请号：US782001

申请日：1997-01-06

申请人： Alan Gatherer ,  Carl E. Lemonds

发明人： Alan Gatherer ,  Carl E. Lemonds

IPC分类号： G06F7/52

CPC分类号： G06F7/5272

摘要： In a multiplier unit having a preprocessor stage, a multiplier stage, and a summation stage, the multiplier stage includes a shift register, a gate component for controllably transmitting the multiplicand A in a manner determined by a bit signal of multiplier B applied to the gate component control terminal. Partial products are grouped by multiplicand digits and each digit is applied, through delay components determined by the order of the digit, to first terminals of an associated adder components. Output signals from each adder component is transmitted through a plurality of delay components and applied to second input terminals of the same adder component. In this manner, partial products A.sub.p *B.sub.q are assembled and the partial products (A.sub.0 + . . . A.sub.M)*B.sub.q =A*B.sub.q can be applied to the summation unit in a single period. When the multiplier is an integer multiple of the multiplicand, the implementation is particularly convenient.

摘要翻译： 在具有预处理器级，乘法器级和求和级的乘法器单元中，乘法器级包括移位寄存器，用于以由施加到门的乘法器B的位信号确定的方式可控地发送被乘数A的门分量 组件控制终端。 部分产品按被乘数分组，每个数字通过由数字顺序确定的延迟分量应用于相关加法器分量的第一个终端。 来自每个加法器分量的输出信号通过多个延迟分量传输并被施加到相同加法器分量的第二输入端。 以这种方式，部分乘积Ap * Bq被组装，并且部分乘积（A0 +。。AM）* Bq = A * Bq可以在单个周期内应用于求和单元。 当乘数是被乘数的整数倍时，实现特别方便。

公开(公告)号：US08868633B2

公开(公告)日：2014-10-21

申请号：US13436555

申请日：2012-03-30

申请人： Carl E. Lemonds ,  Jay E. Fleischman ,  David M. Russinoff

发明人： Carl E. Lemonds ,  Jay E. Fleischman ,  David M. Russinoff

IPC分类号： G06F7/552

CPC分类号： G06F1/03 ,  G06F7/5525 ,  G06F2101/08 ,  G06F2207/5528

摘要： A method, performed by a processor, of determining a square root using a single processor cycle per iteration is described. The method includes, in a single cycle: obtaining, from a stored lookup table, a quotient digit and a square of the quotient digit; retrieving a current solution; and determining a new solution using the current solution and the quotient digit. Circuitry configured to perform the method is described.

摘要翻译： 描述了由处理器执行的使用每个迭代的单个处理器周期来确定平方根的方法。 该方法在单个周期中包括：从存储的查找表中获得商数和商数的平方; 检索当前解决方案; 并使用当前解和商数确定新解。 描述配置为执行该方法的电路。

公开(公告)号：US20130262541A1

公开(公告)日：2013-10-03

申请号：US13436555

申请日：2012-03-30

申请人： Carl E. Lemonds ,  Jay E. Fleischman ,  David M. Russinoff

发明人： Carl E. Lemonds ,  Jay E. Fleischman ,  David M. Russinoff

IPC分类号： G06F1/03

CPC分类号： G06F1/03 ,  G06F7/5525 ,  G06F2101/08 ,  G06F2207/5528

摘要： A method, performed by a processor, of determining a square root using a single processor cycle per iteration is described. The method includes, in a single cycle: obtaining, from a stored lookup table, a quotient digit and a square of the quotient digit; retrieving a current solution; and determining a new solution using the current solution and the quotient digit. Circuitry configured to perform the method is described.

摘要翻译： 描述了由处理器执行的使用每个迭代的单个处理器周期来确定平方根的方法。 该方法在单个周期中包括：从存储的查找表中获得商数和商数的平方; 检索当前解决方案; 并使用当前解和商数确定新解。 描述配置为执行该方法的电路。

公开(公告)号：US5646877A

公开(公告)日：1997-07-08

申请号：US451091

申请日：1995-05-25

申请人： Shivaling Mahant-Shetti ,  Carl E. Lemonds

发明人： Shivaling Mahant-Shetti ,  Carl E. Lemonds

IPC分类号： G06F7/53 ,  G06F7/52 ,  G06F7/525 ,  G06F7/533

CPC分类号： G06F7/5336

摘要： A multiplier and method of multiplying a multiplicand by a multiplier comprising providing a multiplicand of predetermined radix, preferably two, and a predetermined multiple of the multiplicand, preferably three, of the predetermined radix. First and second paths are provided, each path including the multiplicand and the multiple of the multiplicand. One of the multiplicand or multiple of the multiplicand in said first path is selected responsive to the value of the multiplier and one of the multiplicand or multiple of the multiplicand in the second path is selected responsive to the value of the multiplier. The selected multiplicand or multiple of the multiplicand in said first path is left shifted a number of shifts determined by the value of the multiplier and the selected multiplicand or multiple of the multiplicand in the second path is left shifted a number of shifts determined by the value of the multiplier. At least one of the shifted multiplicands or multiples thereof is then assigned one of a positive or negative value as determined by the value of the multiplier and the shifted values are then added together. The circuit also includes an encoder responsive to the value of the multiplier to control the selection of the multiplicand or multiple thereof, the left shifting and the assignment of a positive or negative value. The encoder can include a truth table to assist in performing this function.

摘要翻译： 将被乘数乘以乘法器的乘法器和方法，包括提供预定基数的预定基数，优选为两个的乘法器和预定倍数的预定倍数，优选地三个预定基数。 提供第一和第二路径，每个路径包括被乘数和被乘数的倍数。 响应于乘法器的值来选择所述第一路径中的被乘数之一或被乘数之一，并且响应于乘法器的值来选择第二路径中被乘数中的一个或多个被乘数中的一个。 在所述第一路径中所选择的被乘数或被乘数的倍数是由乘法器的值确定的移位量左移，并且所选择的被乘数或第二路径中被乘数的倍数向左移位由该值确定的多个移位 的乘数。 然后，其中移位的被乘数或其倍数中的至少一个被分配为由乘法器的值确定的正值或负值之一，然后将移位值相加。 电路还包括响应于乘法器的值以控制被乘数或其倍数的选择的编码器，左移位和正值或负值的分配。 编码器可以包括真值表以帮助执行该功能。