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    6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI
    3.
    发明授权
    6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI 失效
    6F2沟槽EDRAM单元，具有双门控垂直MOSFET和自对准STI

    公开(公告)号：US06570208B2

    公开(公告)日：2003-05-27

    申请号：US09766013

    申请日：2001-01-18

    申请人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Gary B. Bronner

    发明人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Gary B. Bronner

    IPC分类号： H01L218242

    CPC分类号： H01L27/10864 ,  H01L21/823481 ,  H01L21/823487

    摘要： A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. The inventive memory cell substantially eliminates the backgating problem and floating well effects that are typically present in prior art memory cells. A method of fabricating the inventive memory cell is also provided.

    摘要翻译： 提供了包含双门控垂直金属氧化物半导体场效应晶体管（MOSFET）和隔离区域（诸如浅沟槽隔离，STI，与电池的字线和位线自对准的区域）的存储单元。 本发明的存储单元基本上消除了现有技术的存储单元中通常存在的背景问题和漂浮阱效应。 还提供了制造本发明的存储单元的方法。

    Static self-refreshing DRAM structure and operating mode
    4.
    发明授权
    Static self-refreshing DRAM structure and operating mode 失效
    静态自刷新DRAM结构和工作模式

    公开(公告)号：US06501117B1

    公开(公告)日：2002-12-31

    申请号：US10007846

    申请日：2001-11-05

    申请人： Carl J. Radens ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Jack A. Mandelman

    发明人： Carl J. Radens ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Jack A. Mandelman

    IPC分类号： H01L27108

    CPC分类号： H01L27/11 ,  G11C11/404 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10867 ,  H01L29/945

    摘要： A DRAM cell storage capacitor is formed above the bottom of a deep trench (DT) below an FET transistor. The DT has upper, central and lower portions with sidewalls. A capacitor plate electrode, surrounding the lower DT portion that is doped with a first dopant type, is separated by an interface from a well region surrounding the upper and central portions of the DT that are doped with an opposite dopant type. A source/drain region formed at the top of the cell is doped with the first dopant type. A node dielectric layer that covers the sidewalls and bottom of the lower and central portions of the DT is filled with a node electrode of the capacitor, doped with the first dopant type, fills the space inside the node dielectric layer in the lower part of the DT. Above a recessed node dielectric layer a strap region space is filled with a buried-strap conductor. An oxide (TTO) layer is formed over the node electrode and the buried-strap in the DT. A peripheral gate oxide layer, which coats sidewalls of the DT above the TTO, defines a space which is filled with the FET gate electrode. An outdiffusion region, doped with the first dopant type, is formed in the well region near the buried-strap. The cell has a first state and an opposite state of operation. A punch-through device, formed in the well between the outdiffusion region and the interface, provides a self-refreshing punchthrough current in the cell between the well and the plate in the first state of cell operation. A reverse bias junction leakage current occurs in the cell between the buried-strap and the P-well to refresh the opposite state of cell operation.

    摘要翻译： 在FET晶体管下方的深沟槽（DT）的底部形成DRAM单元存储电容器。 DT具有具有侧壁的上部，中部和下部。 围绕掺杂有第一掺杂剂类型的下部DT部分的电容器平板电极通过界面与围绕掺杂有相反掺杂剂类型的DT的上部和中部的阱区隔开。 形成在电池顶部的源极/漏极区掺杂有第一掺杂剂类型。 覆盖DT的下部和中心部分的侧壁和底部的节点电介质层填充有掺杂有第一掺杂剂类型的电容器的节点电极，填充第一掺杂剂类型的下部的节点电介质层内部的空间 DT。 在凹陷节点电介质层上方，带区域空间填充有埋地导体。 在DT上的节点电极和掩埋带上形成氧化物（TTO）层。 在TTO上方覆盖DT的侧壁的外围栅极氧化物层限定了用FET栅电极填充的空间。 在掩埋带附近的阱区中形成掺杂有第一掺杂剂类型的扩散区。 电池具有第一状态和相反的操作状态。 形成在扩散区域和界面之间的井中的穿通装置在电池操作的第一状态下在孔和板之间的电池单元中提供自刷新穿透电流。 在埋层和P阱之间的电池中产生反向偏置结漏电流，以刷新电池操作的相反状态。

    Single sided buried strap
    5.
    发明授权
    Single sided buried strap 失效
    单面埋地带

    公开(公告)号：US06426526B1

    公开(公告)日：2002-07-30

    申请号：US09870068

    申请日：2001-05-30

    申请人： Ramachandra Divakaruni ,  Jack A. Mandelman ,  Gary B. Bronner ,  Carl J. Radens

    发明人： Ramachandra Divakaruni ,  Jack A. Mandelman ,  Gary B. Bronner ,  Carl J. Radens

    IPC分类号： H01L27108

    CPC分类号： H01L27/10864

    摘要： An easily manufactured connecting structure from a node conductor of trench capacitor device is characterized at least in part by the presence of an isolation collar located above the node conductor, at least a portion of the collar having an exterior surface which is substantially conformal with at least a portion of an adjacent wall of the trench, a buried strap region in the trench above the node conductor, the strap region being bounded laterally by the isolation collar except at an opening in the collar. The connecting structure is preferably formed by a method involving clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench.

    摘要翻译： 至少部分地由位于节点导体上方的隔离套管的存在而将来自沟槽电容器装置的节点导体的容易制造的连接结构的特征在于，所述套环的至少一部分具有至少基本上保形的外表面 沟槽的相邻壁的一部分，在节点导体上方的沟槽中的掩埋带区域，除了在套环的开口处之外，带区域被隔离套环侧向限定。 连接结构优选地通过一种方法来形成，该方法包括在存储电容器上方的位置处从深沟槽的第一内表面清除隔离套环，同时将隔离套环留在深沟槽的其他表面。

    Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure
    6.
    发明授权
    Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure 失效
    具有垂直MOSFET和埋地位线导体结构的4F2 STC电池的工艺

    公开(公告)号：US06348374B1

    公开(公告)日：2002-02-19

    申请号：US09597887

    申请日：2000-06-19

    申请人： Satish D. Athavale ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

    发明人： Satish D. Athavale ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

    IPC分类号： H01L218242

    CPC分类号： H01L27/10876 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10885

    摘要： A method of forming a vertical transistor. A pad layer is formed over a semiconductor substrate. A trough is formed through the pad layer and in the semiconductor substrate. A bit line is formed buried in the trough. The bit line is enclosed by a dielectric material. A strap is formed extending through the dielectric material to connect the bit line to the semiconductor substrate. The trough is filled above the bit line with a conductor. The conductor is cut along its longitudinal axis such that the conductor remains on one side of the trough. Wordline troughs are formed, substantially orthogonal to the bit line, above the semiconductor substrate. A portion of the conductor is removed under the wordline trough to separate the conductor into separate gate conductors. Wordlines are formed in the wordline trough connected to the separate gate conductors.

    摘要翻译： 一种形成垂直晶体管的方法。 在半导体衬底上形成衬垫层。 通过焊盘层和半导体衬底形成槽。 埋在槽中的位线形成。 位线被电介质材料包围。 形成延伸穿过介电材料的带，以将位线连接到半导体衬底。 槽被填充在位线上方的导体。 导体沿其纵向轴线切割，使得导体保持在槽的一侧。 在半导体衬底之上形成基本上与位线正交的字线槽。 导体的一部分在字线槽下移除，以将导体分离成单独的栅极导体。 字线形成在连接到单独的栅极导体的字线槽中。

    Method of fabricating vertical body-contacted SOI transistor
    7.
    发明授权
    Method of fabricating vertical body-contacted SOI transistor 失效
    垂直体接触SOI晶体管的制造方法

    公开(公告)号：US07759188B2

    公开(公告)日：2010-07-20

    申请号：US12002828

    申请日：2007-12-19

    申请人： Kangguo Cheng ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Carl J. Radens

    发明人： Kangguo Cheng ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Carl J. Radens

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/66666 ,  H01L29/78642

    摘要： A method of fabricating a vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.

    摘要翻译： 提供一种制造垂直场效应晶体管（“FET”）的方法，其包括晶体管本体区域和设置在邻近侧壁的衬底的单晶半导体绝缘体（“SOI”）区域中的源极和漏极区域 的沟渠 衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。 掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。

    Out of the box vertical transistor for eDRAM on SOI
    9.
    发明授权
    Out of the box vertical transistor for eDRAM on SOI 有权
    在SOI上用于eDRAM的开箱式垂直晶体管

    公开(公告)号：US07009237B2

    公开(公告)日：2006-03-07

    申请号：US10709450

    申请日：2004-05-06

    申请人： James W. Adkisson ,  Gary B. Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl J. Radens

    发明人： James W. Adkisson ,  Gary B. Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl J. Radens

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10841 ,  H01L27/10864 ,  H01L27/10867

    摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.

    摘要翻译： 本发明提供了一种形成在绝缘体上硅衬底上的垂直存储器件，其中接触绝缘体上硅衬底的上表面的位线通过上带扩散区域电连接到垂直存储器件 掩埋氧化层。 上带扩散区域通过横向蚀刻掩埋氧化物区域的一部分而形成，其中沉积掺杂多晶硅。 上带区域扩散区域还为垂直存储器件的垂直晶体管提供源极。 垂直存储器件还可以与具有形成在绝缘体上硅衬底上的逻辑器件的支撑区域集成。