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    PACKET SCHEDULING IN A NETWORK PROCESSOR
    1.
    发明申请
    PACKET SCHEDULING IN A NETWORK PROCESSOR 有权
    网络处理器中的分组调度

    公开(公告)号：US20150249604A1

    公开(公告)日：2015-09-03

    申请号：US14193933

    申请日：2014-02-28

    申请人： CAVIUM, INC.

    发明人： Brian Robert Folsom ,  Joseph B. Tompkins ,  Wilson P. Snyder, II ,  Richard E. Kessler ,  Edwin Langevin ,  Andrew J. Jones ,  Ethan F. Robbins

    IPC分类号： H04L12/741 ,  H04L12/911 ,  H04L29/06 ,  H04L12/721

    CPC分类号： H04L45/74 ,  H04L45/36 ,  H04L45/566 ,  H04L47/821 ,  H04L49/25 ,  H04L69/22

    摘要： A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE models the packet through a model of the network topology, determining an order in which to transmit the packet among a number of packets based on the modeling. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.

    摘要翻译： 电路用于管理网络分组处理器中的分组的传送。 该电路包括分组描述符管理器（PDM），分组调度引擎（PSE）以及分组引擎和缓冲模块（PEB）。 PDM从命令信号生成元包和描述符，其中命令信号标识要由电路发送的分组。 PSE通过网络拓扑的模型对分组进行建模，根据建模确定在多个分组之间传输分组的顺序。 一旦分组被安排传输，PEB就根据描述符中指示的指令对分组执行处理操作以产生处理的分组。 然后，PEB使处理的分组被发送到目的地。

    PACKET SHAPING IN A NETWORK PROCESSOR
    3.
    发明申请
    PACKET SHAPING IN A NETWORK PROCESSOR 有权
    网络处理器中的分组形式

    公开(公告)号：US20150249620A1

    公开(公告)日：2015-09-03

    申请号：US14194038

    申请日：2014-02-28

    申请人： Cavium, Inc.

    发明人： Brian Robert Folsom ,  Joseph B. Tompkins ,  Wilson P. Snyder, II ,  Richard E. Kessler ,  Edwin Langevin ,  Andrew J. Jones ,  Ethan F. Robbins

    IPC分类号： H04L12/911 ,  H04L12/741 ,  H04L29/06 ,  H04L12/721

    CPC分类号： H04L47/821 ,  G06F13/42 ,  H04L45/566 ,  H04L45/74 ,  H04L49/90 ,  H04L69/22

    摘要： A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE compares a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet, and determines an order in which to transmit the packet among a number of packets based on the comparison. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.

    摘要翻译： 电路用于管理网络分组处理器中的分组的传送。 该电路包括分组描述符管理器（PDM），分组调度引擎（PSE）以及分组引擎和缓冲模块（PEB）。 PDM从命令信号生成元包和描述符，其中命令信号标识要由电路发送的分组。 PSE与分组相关联的分组传输速率与峰值速率和与分组相关联的承诺速率中的至少一个进行比较，并且基于比较确定在多个分组之间传送分组的顺序。 一旦分组被安排传输，PEB就根据描述符中指示的指令对分组执行处理操作以产生处理的分组。 然后，PEB使处理的分组被发送到目的地。

    Packet shaping in a network processor
    4.
    发明授权
    Packet shaping in a network processor 有权
    网络处理器中的数据包整形

    公开(公告)号：US09559982B2

    公开(公告)日：2017-01-31

    申请号：US14194038

    申请日：2014-02-28

    申请人： Cavium, Inc.

    发明人： Brian Robert Folsom ,  Joseph B. Tompkins ,  Wilson P. Snyder, II ,  Richard E. Kessler ,  Edwin Langevin ,  Andrew J. Jones ,  Ethan F. Robbins

    IPC分类号： H04L12/28 ,  H04L12/56 ,  H04L12/911 ,  H04L12/721 ,  H04L12/741 ,  H04L29/06 ,  G06F13/42 ,  H04L12/861

    CPC分类号： H04L47/821 ,  G06F13/42 ,  H04L45/566 ,  H04L45/74 ,  H04L49/90 ,  H04L69/22

    摘要： A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE compares a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet, and determines an order in which to transmit the packet among a number of packets based on the comparison. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.

    摘要翻译： 电路用于管理网络分组处理器中的分组的传送。 该电路包括分组描述符管理器（PDM），分组调度引擎（PSE）以及分组引擎和缓冲模块（PEB）。 PDM从命令信号生成元包和描述符，其中命令信号标识要由电路发送的分组。 PSE与分组相关联的分组传输速率与峰值速率和与分组相关联的承诺速率中的至少一个进行比较，并且基于比较确定在多个分组之间传送分组的顺序。 一旦分组被安排传输，PEB就根据描述符中指示的指令对分组执行处理操作以产生处理的分组。 然后，PEB使处理的分组被发送到目的地。

    Packet scheduling in a network processor
    5.
    发明授权
    Packet scheduling in a network processor 有权
    网络处理器中的分组调度

    公开(公告)号：US09397938B2

    公开(公告)日：2016-07-19

    申请号：US14193933

    申请日：2014-02-28

    申请人： Cavium, Inc.

    发明人： Brian Robert Folsom ,  Joseph B. Tompkins ,  Wilson P. Snyder, II ,  Richard E. Kessler ,  Edwin Langevin ,  Andrew J. Jones ,  Ethan F. Robbins

    IPC分类号： H04L12/28 ,  H04L12/56 ,  H04L12/741 ,  H04L12/721 ,  H04L12/911 ,  H04L29/06 ,  H04L12/947

    CPC分类号： H04L45/74 ,  H04L45/36 ,  H04L45/566 ,  H04L47/821 ,  H04L49/25 ,  H04L69/22

    摘要： A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE models the packet through a model of the network topology, determining an order in which to transmit the packet among a number of packets based on the modeling. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.

    摘要翻译： 电路用于管理网络分组处理器中的分组的传送。 该电路包括分组描述符管理器（PDM），分组调度引擎（PSE）以及分组引擎和缓冲模块（PEB）。 PDM从命令信号生成元包和描述符，其中命令信号标识要由电路发送的分组。 PSE通过网络拓扑的模型对分组进行建模，根据建模确定在多个分组之间传输分组的顺序。 一旦分组被安排传输，PEB就根据描述符中指示的指令对分组执行处理操作以产生处理的分组。 然后，PEB使处理的分组被发送到目的地。

    PACKET OUTPUT PROCESSING
    6.
    发明申请
    PACKET OUTPUT PROCESSING 有权
    分组输出处理

    公开(公告)号：US20150249603A1

    公开(公告)日：2015-09-03

    申请号：US14193895

    申请日：2014-02-28

    申请人： Cavium, Inc.

    发明人： Joseph B. Tompkins ,  Brian Robert Folsom ,  Wilson P. Snyder, II ,  Richard E. Kessler ,  Edwin Langevin ,  Andrew J. Jones ,  Ethan F. Robbins ,  Krupa Sagar O.S. Mylavarapu ,  Mahesh Dorai ,  Nagaraj G. Shirali ,  Ranjith Kumar V. Hallur

    IPC分类号： H04L12/741 ,  H04L12/911 ,  H04L12/721 ,  H04L29/06

    CPC分类号： H04L45/74 ,  H04L45/566 ,  H04L47/32 ,  H04L47/34 ,  H04L47/50 ,  H04L47/6225 ,  H04L47/821 ,  H04L69/22

    摘要： A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE determines an order in which to transmit the packet among a number of packets, where the PSE determines the order based on information indicated in the metapacket. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.

    摘要翻译： 电路用于管理网络分组处理器中的分组的传送。 该电路包括分组描述符管理器（PDM），分组调度引擎（PSE）以及分组引擎和缓冲模块（PEB）。 PDM从命令信号生成元包和描述符，其中命令信号标识要由电路发送的分组。 PSE确定在多个分组之间发送分组的顺序，其中PSE基于元包中指示的信息来确定顺序。 一旦分组被安排传输，PEB就根据描述符中指示的指令对分组执行处理操作以产生处理的分组。 然后，PEB使处理的分组被发送到目的地。