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    Method and apparatus for memory allocation in a multi-node system
    3.
    发明授权
    Method and apparatus for memory allocation in a multi-node system 有权
    多节点系统中存储器分配的方法和装置

    公开(公告)号：US09529532B2

    公开(公告)日：2016-12-27

    申请号：US14201594

    申请日：2014-03-07

    申请人： Cavium, Inc.

    发明人： Richard E. Kessler ,  Wilson P. Snyder, II

    IPC分类号： G06F3/06 ,  G06F13/16

    CPC分类号： G06F3/0608 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1657

    摘要： According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of memory allocation in the multi-chip system comprises managing, by each of one or more free-pool allocator (FPA) coprocessors in the multi-chip system, a corresponding list of pools of free-buffer pointers. Based on the one or more lists of free-buffer pointers managed by the one or more FPA coprocessors, a memory allocator (MA) hardware component allocates a free buffer, associated with a chip device of the multiple chip devices, to data associated with a work item. According to at least one aspect, the data associated with the work item represents a data packet.

    摘要翻译： 根据至少一个示例性实施例，多芯片系统包括被配置为彼此通信并共享资源的多个芯片装置。 根据至少一个示例实施例，多芯片系统中的存储器分配的方法包括通过多芯片系统中的一个或多个空闲池分配器（FPA）协处理器中的每一个来管理相应的免费池池列表 缓存指针 基于由一个或多个FPA协处理器管理的一个或多个空闲缓冲器指针列表，存储器分配器（MA）硬件组件将与多个芯片设备的芯片设备相关联的空闲缓冲区分配给与 工作项目。 根据至少一个方面，与工作项相关联的数据表示数据分组。

    Method and apparatus for supporting wide operations using atomic sequences
    4.
    发明授权
    Method and apparatus for supporting wide operations using atomic sequences 有权
    使用原子序列支持广泛操作的方法和装置

    公开(公告)号：US09501243B2

    公开(公告)日：2016-11-22

    申请号：US14045602

    申请日：2013-10-03

    申请人： Cavium, Inc.

    发明人： Richard E. Kessler ,  Michael S. Bertone ,  Christopher J. Comis

    IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F9/30

    CPC分类号： G06F3/0656 ,  G06F3/0614 ,  G06F3/0671 ,  G06F9/3004 ,  G06F9/30072

    摘要： Implementations of wide atomic sequences are achieved by augmenting a load operation designed to initiate an atomic sequence and augmenting a conditional storing operation that typically terminates the atomic sequence. The augmented load operation is designed to further allocate a memory buffer besides initiating the atomic sequence. The conditional storing operation is augmented to check the allocated memory buffer for any data stored therein. If one or more data words are detected in the memory buffer, the conditional storing operation stores the detected data word(s) and another word provided as operand in a concatenation of memory locations. The achieved wide atomic sequences enable the hardware system to support wide memory operations and wide operations in general.

    摘要翻译： 宽原子序列的实现通过增加设计用于发起原子序列的负载操作和扩充典型地终止原子序列的条件存储操作来实现。 增强负载操作被设计为除了启动原子序列之外还进一步分配存储器缓冲器。 增加条件存储操作以检查分配的存储器缓冲器中存储的任何数据。 如果在存储器缓冲器中检测到一个或多个数据字，则条件存储操作将检测到的数据字和作为操作数提供的另一个字存储在存储器位置的级联中。 实现的宽原子序列使硬件系统能够支持广泛的存储器操作和广泛的操作。

    Register Access Control Among Multiple Devices
    5.
    发明申请
    Register Access Control Among Multiple Devices 有权
    注册多个设备之间的访问控制

    公开(公告)号：US20160140065A1

    公开(公告)日：2016-05-19

    申请号：US14540414

    申请日：2014-11-13

    申请人： Cavium, Inc.

    发明人： Robert A. Sanzone ,  Wilson P. Snyder, II ,  Richard E. Kessler

    IPC分类号： G06F13/364 ,  G06F13/37 ,  G06F13/42

    CPC分类号： G06F13/364 ,  G06F13/37 ,  G06F13/4282

    摘要： A circuit manages and controls access requests to a register, such as a control and status register (CSR) among a number of devices. In particular, the circuit selectively forwards or suspends off-chip access requests and forwards on-chip access requests independent of the status of off-chip requests. The circuit receives access requests at a plurality of buses, one or more of which can be dedicated to exclusively on-chip requests and/or exclusively off-chip requests. Based on the completion status of previous off-chip access requests, further off-chip access requests are selectively forwarded or suspended, while on-chip access request are sent independently of off-chip request status.

    摘要翻译： 电路管理和控制对诸如多个设备之间的控制和状态寄存器（CSR）的寄存器的访问请求。 特别地，电路选择性地转发或暂停片外访问请求，并转发独立于片外请求状态的片上访问请求。 电路在多个总线上接收访问请求，其中一个或多个可以专用于专用片上请求和/或专用片外请求。 基于先前的片外访问请求的完成状态，选择性地转发或暂停进一步的片外访问请求，而独立于片外请求状态发送片上访问请求。

    Maintenance of cache and tags in a translation lookaside buffer
    6.
    发明授权
    Maintenance of cache and tags in a translation lookaside buffer 有权
    在翻译后备缓冲区中维护缓存和标签

    公开(公告)号：US09268694B2

    公开(公告)日：2016-02-23

    申请号：US14038225

    申请日：2013-09-26

    申请人： Cavium, Inc.

    发明人： Wilson P. Snyder, II ,  Bryan W. Chin ,  Shubhendu S. Mukherjee ,  Michael Bertone ,  Richard E. Kessler

    IPC分类号： G06F13/12 ,  G06F12/08 ,  G06F12/10

    CPC分类号： G06F12/0808 ,  G06F12/0802 ,  G06F12/0888 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/1045 ,  G06F2212/151 ,  G06F2212/681

    摘要： A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB is an additional cache storing collapsed translations derived from the MTLB. Entries in the MTLB, the collapsed TLB, and other caches can be maintained for consistency.

    摘要翻译： 支持虚拟化的计算机系统可以维护多个地址空间。 每个客户操作系统都使用客户虚拟地址（GVAs），将其转换为访客物理地址（GPAs）。 管理一个或多个客户机操作系统的管理程序将GPA转换为根物理地址（RPAs）。 合并的翻译后备缓冲区（MTLB）缓存多个寻址域之间的转换，实现更快的地址转换和存储器访问。 MTLB可以作为多个不同的缓存在逻辑上可寻址，并且可以被重新配置为向每个逻辑高速缓存分配不同的空间。 此外，折叠TLB是从MTLB导出的附加高速缓存存储折叠的折叠。 MTLB中的条目，折叠的TLB和其他高速缓存可以保持一致。

    Translation bypass in multi-stage address translation
    8.
    发明授权
    Translation bypass in multi-stage address translation 有权
    翻译绕过多级地址转换

    公开(公告)号：US09208103B2

    公开(公告)日：2015-12-08

    申请号：US14038383

    申请日：2013-09-26

    申请人： Cavium, Inc.

    发明人： Richard E. Kessler ,  Bryan W. Chin ,  Michael Bertone

    IPC分类号： G06F13/12 ,  G06F12/10 ,  G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/1045 ,  G06F12/00 ,  G06F12/0802 ,  G06F12/0808 ,  G06F12/0888 ,  G06F12/1027 ,  G06F12/1036

    摘要： A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Lookups to the caches of the MTLB can be selectively bypassed based on a control configuration and the attributes of a received address.

    摘要翻译： 支持虚拟化的计算机系统可以维护多个地址空间。 每个客户操作系统都使用客户虚拟地址（GVAs），将其转换为访客物理地址（GPAs）。 管理一个或多个客户机操作系统的管理程序将GPA转换为根物理地址（RPAs）。 合并的翻译后备缓冲区（MTLB）缓存多个寻址域之间的转换，实现更快的地址转换和存储器访问。 MTLB可以作为多个不同的缓存在逻辑上可寻址，并且可以被重新配置为向每个逻辑高速缓存分配不同的空间。 可以基于控制配置和接收到的地址的属性来选择性地旁路对MTLB的高速缓存的查找。

    MULTI-CORE NETWORK PROCESSOR INTERCONNECT WITH MULTI-NODE CONNECTION
    9.
    发明申请
    MULTI-CORE NETWORK PROCESSOR INTERCONNECT WITH MULTI-NODE CONNECTION 审中-公开
    多核心网络处理器与多节点连接相互连接

    公开(公告)号：US20150254182A1

    公开(公告)日：2015-09-10

    申请号：US14201507

    申请日：2014-03-07

    申请人： Cavium, Inc.

    发明人： David H. Asher ,  Richard E. Kessler ,  Bradley D. Dobbie ,  Isam Akkawi ,  John M. Perveiler ,  Georgios Faldamis ,  Charles M. Oliveira

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0833 ,  G06F9/546 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0891

    摘要： According to at least one example embodiment, a method of data coherence is employed within a multi-chip system to enforce cache coherence between chip devices of the multi-node system. According at least one example embodiment, a message is received by a first chip device of the multiple chip devices from a second chip device of the multiple chip devices. The message triggers invalidation of one or more copies, if any, of a data block. The data block stored in a memory attached to, or residing in, the first chip device. Upon determining that one or more remote copies of the data block are stored in one or more other chip devices, other than the first chip device, the first chip device sends one or more invalidation requests to the one or more other chip devices for invalidating the one or more remote copies of the data block.

    摘要翻译： 根据至少一个示例性实施例，在多芯片系统内采用数据一致性的方法来实现多节点系统的芯片装置之间的高速缓存一致性。 根据至少一个示例性实施例，消息由多个芯片装置的第二芯片装置由多个芯片装置的第一芯片装置接收。 该消息触发数据块的一个或多个副本（如果有）的无效。 存储在连接到或驻留在第一芯片装置中的存储器中的数据块。 在确定数据块的一个或多个远程副本被存储在除了第一芯片装置之外的一个或多个其他芯片装置中时，第一芯片装置向一个或多个其他芯片装置发送一个或多个无效请求，使无效的 数据块的一个或多个远程副本。

    METHOD AND SYSTEM FOR WORK SCHEDULING IN A MULTI-CHIP SYSTEM
    10.
    发明申请
    METHOD AND SYSTEM FOR WORK SCHEDULING IN A MULTI-CHIP SYSTEM 有权
    多芯片系统中的工作调度方法与系统

    公开(公告)号：US20150254104A1

    公开(公告)日：2015-09-10

    申请号：US14201541

    申请日：2014-03-07

    申请人： Cavium, Inc.

    发明人： Richard E. Kessler ,  Wilson P. Snyder, II

    IPC分类号： G06F9/48 ,  G06F12/02

    CPC分类号： G06F9/4881 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0656 ,  G06F3/0673 ,  G06F9/5016 ,  G06F9/5072 ,  G06F12/023 ,  G06F2209/486 ,  G06F2212/1044

    摘要： According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share hardware resources. According to at least one example embodiment, a method of processing work item in the multi-chip system comprises designating, by a work source component associated with a chip device, referred to as the source chip device, of the multiple chip devices, a work item to a scheduler for scheduling. The scheduler then assigns the work item to a another chip device, referred to as the destination chip device, of the multiple chip devices for processing, the scheduler is one of one or more schedulers each associated with a corresponding chip device of the multiple chip devices.

    摘要翻译： 根据至少一个示例性实施例，多芯片系统包括被配置为彼此通信并共享硬件资源的多个芯片装置。 根据至少一个示例性实施例，一种在多芯片系统中处理工作项的方法包括：通过与芯片装置相关的工作源组件（被称为源芯片装置）指定多个芯片装置，工作 项目到调度程序进行调度。 调度器然后将工作项目分配给用于处理的多个芯片装置的称为目标芯片装置的另一芯片装置，调度器是每个与多个芯片装置的相应芯片装置相关联的一个或多个调度器之一 。