公开(公告)号：US12105625B2

公开(公告)日：2024-10-01

申请号：US17588240

申请日：2022-01-29

申请人： Ceremorphic, Inc.

发明人： Lizy Kurian John ,  Venkat Mattela ,  Heonchul Park

IPC分类号： G06F12/04 ,  G06N3/0464 ,  G06N3/10

CPC分类号： G06F12/04 ,  G06N3/0464 ,  G06N3/10 ,  G06F2212/16

摘要： A programmable address generator has an iteration variable generator for generation of an ordered set of iteration variables, which are re-ordered by an iteration variable selection fabric, which delivers the re-ordered iteration variables to one or more address generators. A configurator receives an instruction containing fields which provide configuration constants to the address generator, iteration variable selection fabric, and address generators. After configuration, the address generators provide addresses coupled to a memory. In one example of the invention, the address generators generate an input address, a coefficient address, and an output address for performing convolutional neural network inferences.

公开(公告)号：US12072799B2

公开(公告)日：2024-08-27

申请号：US18121294

申请日：2023-03-14

申请人： CEREMORPHIC, INC.

发明人： Lizy Kurian John ,  Venkat Mattela ,  Heonchul Park

IPC分类号： G06F12/04 ,  G06N3/0464 ,  G06N3/10

CPC分类号： G06F12/04 ,  G06N3/0464 ,  G06N3/10 ,  G06F2212/16

摘要： A programmable address generator has an iteration variable generator for generation of an ordered set of iteration variables, which are re-ordered by an iteration variable selection fabric, which delivers the re-ordered iteration variables to one or more address generators. A configurator receives an instruction containing fields which provide configuration constants to the address generator, iteration variable selection fabric, and address generators. After configuration, the address generators provide addresses coupled to a memory. In one example of the invention, the address generators generate an input address, a coefficient address, and an output address for performing convolutional neural network inferences.

公开(公告)号：US12111913B2

公开(公告)日：2024-10-08

申请号：US17485436

申请日：2021-09-26

申请人： Ceremorphic, Inc.

发明人： Lizy Kurian John ,  Heonchul Park ,  Venkat Mattela

IPC分类号： G06F21/52 ,  G06F9/30

CPC分类号： G06F21/52 ,  G06F9/3001 ,  G06F9/30076 ,  G06F2221/033

摘要： A secure processor with fault detection has a core thread which executes with a redundant branch processor thread. In one configuration, the core thread is operative on a fully functional core processor configured to execute a complete instruction set, and the redundant branch processor thread contains only initialization instructions and flow control instructions such as branch instructions and is operative on a redundant branch processor which is configured to execute a subset of the complete instruction set, specifically a branch control variable initialization and a branch instruction, thereby greatly simplifying the redundant branch processor architecture. Fault conditions are detected by comparing either a history of branch taken/not taken and branch targets, or a comparison of program counter activity for the core thread and redundant branch processor thread.

公开(公告)号：US12026093B1

公开(公告)日：2024-07-02

申请号：US17883249

申请日：2022-08-08

申请人： Ceremorphic, Inc.

发明人： Lizy Kurian John ,  Venkat Mattela ,  Heonchul Park

IPC分类号： G06F12/08 ,  G06F12/0802 ,  G06F12/1009

CPC分类号： G06F12/0802 ,  G06F12/1009 ,  G06F2212/60

摘要： A data storage system has a CPU data bus for reading and writing data to data accelerators. Each data accelerator has a controller which receives the read and write requests and determines whether to read or write a local cache memory in preprocessed form or an attached accelerator memory which has greater size capacity based on entries in an address translation table (ATT) and saves data in a raw unprocessed form. The controller may also include an address translation table for mapping input addresses to memory addresses and indicating the presence of data in preprocessed form.

公开(公告)号：US11921843B2

公开(公告)日：2024-03-05

申请号：US17485471

申请日：2021-09-26

申请人： Ceremorphic, Inc.

发明人： Lizy Kurian John ,  Heonchul Park ,  Venkat Mattela

IPC分类号： G06F11/16 ,  G06F9/38 ,  G06F21/52

CPC分类号： G06F21/52 ,  G06F9/3804 ,  G06F11/1629 ,  G06F2221/033

摘要： A fault detecting multi-thread pipeline processor with fault detection is operative with a single pipeline stage which generates branch status comprising at least one of branch taken/not_taken, branch direction, and branch target. A first thread has control and data instructions, the control instructions comprising loop instructions including unconditional and conditional branch instructions, loop initialization instructions, loop arithmetic instructions, and no operation (NOP) instructions. A second thread has only control instructions and either has the non-control instructions replaced with NOP instructions, or removed entirely. A fault detector compares the branch status of the first thread and second thread and asserts a fault output when they do not match.