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公开(公告)号：US12143313B1
公开(公告)日：2024-11-12
申请号：US17671569
申请日：2022-02-14
Applicant: Ceremorphic, Inc.
Inventor： Suyash Kandele , Sumant Kumar Singh , Joydeep Kumar Devnath , Venkat Mattela , Govardhan Mattela , Heonchul Park
IPC: H04L49/1546 , H04L49/00
Abstract: A system and method for a switching network is disclosed. A plurality of first switching assemblies, second switching assemblies and intermediate switching assemblies with each of the first switching assemblies, second switching assemblies and intermediate switching assemblies having at least two input ports and output ports is provided. Selective one of the two input ports is configured to receive a data to be processed and delivered at a designated one of the output ports. Received data passes through one or more selective first switching assemblies, one or more intermediate switching assemblies and one or more selective second switching assemblies, before the received data is delivered to the designated port. A plurality of additional data is received in one or more of the input ports to be delivered to one or more designated output ports is processed before the received data is delivered to the designated one of the output ports.
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公开(公告)号：US11928475B2
公开(公告)日：2024-03-12
申请号：US17519588
申请日：2021-11-05
Applicant: Ceremorphic, Inc.
Inventor： Heonchul Park
CPC classification number: G06F9/3869 , G06F11/1629 , G06F11/1695
Abstract: An exemplary fault-tolerant computing system comprises a secondary processor configured to execute in delayed lock step with a primary processor from a common program store, comparators in the store data and writeback paths to detect a fault based on comparing primary and secondary processor states, and a writeback path delay permitting aborting execution when a fault is detected, before writeback of invalid data. The secondary processor execution and the primary processor store data and writeback may be delayed a predetermined number of cycles, permitting fault detection before writing invalid data. Store data and writeback paths may include triple module redundancy configured to pass only majority data through the store data and writeback path delay stages. Some implementations may forward data from the store data path delay stages to the writeback stage or memory if the load data address matches the address of data in a store data path delay stage.
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公开(公告)号：US12242849B1
公开(公告)日：2025-03-04
申请号：US18238479
申请日：2023-08-26
Applicant: Ceremorphic, Inc.
Inventor： Heonchul Park , Venkat Mattela
Abstract: A computing system includes (1) a primary processor executing executable instructions and generating first instruction data associated with the executable instructions, (2) a secondary processor executing the executable instructions one or more clock cycles behind the primary processor and generating secondary instruction data associated with the executable instructions, (3) a first first-in first-out (FIFO) buffer for the primary processor, (4) a second FIFO buffer for the secondary processor, (5) circuitry storing at least some of the first instruction data in the first FIFO buffer and at least some of the second instruction data in the second FIFO buffer, (6) compare circuitry comparing a first portion of first instruction data and a second portion of second instruction data that are associated with a given clock cycle, and (7) control circuitry halting the primary and secondary processors responsive to a mismatch between the first portion and the second portion.
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公开(公告)号：US12106110B2
公开(公告)日：2024-10-01
申请号：US17463535
申请日：2021-08-31
Applicant: Ceremorphic, Inc.
Inventor： Heonchul Park
IPC: G06F9/38 , G06F1/04 , G06F12/0875
CPC classification number: G06F9/3802 , G06F1/04 , G06F9/3851 , G06F9/3861 , G06F12/0875 , G06F2212/452
Abstract: Embodiments are provided for instructions cache system for a hardware multi-thread microprocessor. In some embodiments, a cache controller device includes multiple interfaces connected to a hardware multi-thread microprocessor. A first interface of the multiple interfaces can receive a fetch request from a first execution thread during a first clock cycle. A second interface of the multiple interfaces can receive a fetch request from a second execution thread during a second clock cycle after the first clock cycle. The cache controller device also includes a multiplexer to send first response signals in response to the fetch request from the first execution thread, and also to send second response signals in response to the fetch request from the second execution thread.
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公开(公告)号：US20230098640A1
公开(公告)日：2023-03-30
申请号：US17485436
申请日：2021-09-26
Applicant: Ceremorphic, Inc.
Inventor： Lizy Kurian JOHN , Heonchul Park , Venkat MATTELA
Abstract: A secure processor with fault detection has a core thread which executes with a redundant branch processor thread. In one configuration, the core thread is operative on a fully functional core processor configured to execute a complete instruction set, and the redundant branch processor thread contains only initialization instructions and flow control instructions such as branch instructions and is operative on a redundant branch processor which is configured to execute a subset of the complete instruction set, specifically a branch control variable initialization and a branch instruction, thereby greatly simplifying the redundant branch processor architecture. Fault conditions are detected by comparing either a history of branch taken/not taken and branch targets, or a comparison of program counter activity for the core thread and redundant branch processor thread.
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Patent Agency Ranking
公开(公告)号：US12111913B2
公开(公告)日：2024-10-08
申请号：US17485436
申请日：2021-09-26
Applicant: Ceremorphic, Inc.
Inventor： Lizy Kurian John , Heonchul Park , Venkat Mattela
CPC classification number: G06F21/52 , G06F9/3001 , G06F9/30076 , G06F2221/033
Abstract: A secure processor with fault detection has a core thread which executes with a redundant branch processor thread. In one configuration, the core thread is operative on a fully functional core processor configured to execute a complete instruction set, and the redundant branch processor thread contains only initialization instructions and flow control instructions such as branch instructions and is operative on a redundant branch processor which is configured to execute a subset of the complete instruction set, specifically a branch control variable initialization and a branch instruction, thereby greatly simplifying the redundant branch processor architecture. Fault conditions are detected by comparing either a history of branch taken/not taken and branch targets, or a comparison of program counter activity for the core thread and redundant branch processor thread.
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公开(公告)号：US12026093B1
公开(公告)日：2024-07-02
申请号：US17883249
申请日：2022-08-08
Applicant: Ceremorphic, Inc.
Inventor： Lizy Kurian John , Venkat Mattela , Heonchul Park
IPC: G06F12/08 , G06F12/0802 , G06F12/1009
CPC classification number: G06F12/0802 , G06F12/1009 , G06F2212/60
Abstract: A data storage system has a CPU data bus for reading and writing data to data accelerators. Each data accelerator has a controller which receives the read and write requests and determines whether to read or write a local cache memory in preprocessed form or an attached accelerator memory which has greater size capacity based on entries in an address translation table (ATT) and saves data in a raw unprocessed form. The controller may also include an address translation table for mapping input addresses to memory addresses and indicating the presence of data in preprocessed form.
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公开(公告)号：US11940945B2
公开(公告)日：2024-03-26
申请号：US17566848
申请日：2021-12-31
Applicant: CEREMORPHIC, INC.
Inventor： Heonchul Park
CPC classification number: G06F15/8007 , G06F9/382 , G06F15/7889
Abstract: An exemplary SIMD computing system comprises a SIMD processing element (SPE) configured to perform a selected operation on a portion of a processor input data word, with the operation selected by control signals read from a control memory location addressed by a decoded instruction. The SPE may comprise one or more adder, multiplier, or multiplexer coupled to the control signals. The control signals may comprise one or more bit read from the control memory. The control memory may be an M×N (M rows by N columns) memory having M possible SIMD operations and N control signals. Each instruction decoded may select an SPE operation from among N rows. A plurality of SPEs may receive the same control signals. The control memory may be rewritable, advantageously permitting customizable SIMD operations that are reconfigurable by storing in the control memory locations control signals designed to cause the SPE to perform selected operations.
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公开(公告)号：US11921843B2
公开(公告)日：2024-03-05
申请号：US17485471
申请日：2021-09-26
Applicant: Ceremorphic, Inc.
Inventor： Lizy Kurian John , Heonchul Park , Venkat Mattela
CPC classification number: G06F21/52 , G06F9/3804 , G06F11/1629 , G06F2221/033
Abstract: A fault detecting multi-thread pipeline processor with fault detection is operative with a single pipeline stage which generates branch status comprising at least one of branch taken/not_taken, branch direction, and branch target. A first thread has control and data instructions, the control instructions comprising loop instructions including unconditional and conditional branch instructions, loop initialization instructions, loop arithmetic instructions, and no operation (NOP) instructions. A second thread has only control instructions and either has the non-control instructions replaced with NOP instructions, or removed entirely. A fault detector compares the branch status of the first thread and second thread and asserts a fault output when they do not match.
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公开(公告)号：US20230409329A1
公开(公告)日：2023-12-21
申请号：US17829050
申请日：2022-05-31
Applicant: Ceremorphic, Inc.
IPC: G06F9/38
CPC classification number: G06F9/3802 , G06F9/3851
Abstract: A master processor is configured to execute a first thread and a second thread designated to run a program in sequence. A slave processor is configured to execute a third thread to run the program in sequence. An instruction fetch compare engine is provided. The first thread initiates a first thread instruction fetch for the program and stored in an instruction fetch storage. Retrieved data associated with the fetched first thread instruction is stored in a retrieved data storage. The second thread initiates a second thread instruction fetch for the program. The instruction fetch compare logic compares the second thread instruction fetch for the program with the first thread instruction fetch stored in the instruction fetch storage for a match. When there is a match, the retrieved data associated with the fetched first thread instruction is presented from the retrieved data storage, in response to the second thread instruction fetch.
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