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公开(公告)号：US12041159B2
公开(公告)日：2024-07-16
申请号：US17683087
申请日：2022-02-28
申请人： Ceremorphic, Inc.
发明人： Suyash Kandele , Joydeep Kumar Devnath , Mohammed Sumair , Ananya Shrivastava , Govardhan Mattela
CPC分类号： H04L9/0618 , H04L9/14
摘要： A cryptographic method includes (1) with the first chiplet, parsing a message into one or more message blocks (2) dynamically generating a first target value that is associated with a first key (3) dynamically generating a second target value that is associated with a second key (4) encrypting at least one message block of the at least one or more message blocks to generate some ciphertext, the encryption being performed with at least one operation that includes at least one XOR operation, the at least one XOR operation performed at least in part with the first target value and with at least the second target value, the first target value and the second target value being accessed via the first and second keys, respectively; and (5) with at least one processing device associated with the first chiplet, transmitting the some ciphertext to a second chiplet.
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公开(公告)号：US11971448B2
公开(公告)日：2024-04-30
申请号：US18144848
申请日：2023-05-09
申请人： Ceremorphic, Inc.
发明人： Robert F. Wiser , Shakti Singh , Neelam Surana
IPC分类号： G01R31/3185 , G01R31/317 , G01R31/319 , H03K3/037 , H03K3/3562
CPC分类号： G01R31/318541 , G01R31/31723 , G01R31/318572 , G01R31/31924 , H03K3/0372 , H03K3/35625 , G01R31/318583
摘要： A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.
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公开(公告)号：US11962298B1
公开(公告)日：2024-04-16
申请号：US17829091
申请日：2022-05-31
申请人： Ceremorphic, Inc.
CPC分类号： H03K19/18 , H01F10/324 , H03K19/173 , H10N35/00 , H10N50/20 , H10N50/85
摘要： A system and method for a logic device is disclosed. A first substrate, and a second substrate is provided, which are spaced apart from each other and manifests Spin orbit torque effect. A nanomagnet is disposed over the first substrate and the second substrate. A first charge current is passed through the first substrate and a second charge current is passed through the second substrate. A direction of flow of the first charge current and the second charge current defines an input value of either a first value or a second value. A spin in the nanomagnet is selectively oriented based on the direction of flow of the first charge current and the second charge current. The spin in the nanomagnet is selectively read to determine an output value as the first value or the second value. The logic device is configured as a XOR logic.
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公开(公告)号：US11936504B1
公开(公告)日：2024-03-19
申请号：US17829070
申请日：2022-05-31
申请人： Ceremorphic, Inc.
IPC分类号： H04L25/03
CPC分类号： H04L25/03025 , H04L25/03885 , H04L2025/0349
摘要： A decision feedback equalizer includes a summer, a slicer, and a feedback circuit. The summer is configured to receive an input signal and a correction signal from the feedback circuit and generate a summer output signal. The slicer includes a first slicer and a second slicer, both are configured to receive the summer output signal as an input, and output a slicer output signal. The feedback circuit is configured to receive the slicer output signal, and based on the slicer output signal, generate the correction signal. The input signal is received at a first clock rate. The first slicer and the second slicer sample the input signal at a second clock rate, about half the first clock rate.
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公开(公告)号：US11928475B2
公开(公告)日：2024-03-12
申请号：US17519588
申请日：2021-11-05
申请人： Ceremorphic, Inc.
发明人： Heonchul Park
CPC分类号： G06F9/3869 , G06F11/1629 , G06F11/1695
摘要： An exemplary fault-tolerant computing system comprises a secondary processor configured to execute in delayed lock step with a primary processor from a common program store, comparators in the store data and writeback paths to detect a fault based on comparing primary and secondary processor states, and a writeback path delay permitting aborting execution when a fault is detected, before writeback of invalid data. The secondary processor execution and the primary processor store data and writeback may be delayed a predetermined number of cycles, permitting fault detection before writing invalid data. Store data and writeback paths may include triple module redundancy configured to pass only majority data through the store data and writeback path delay stages. Some implementations may forward data from the store data path delay stages to the writeback stage or memory if the load data address matches the address of data in a store data path delay stage.
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公开(公告)号：US11922240B2
公开(公告)日：2024-03-05
申请号：US17139226
申请日：2020-12-31
申请人： Ceremorphic, Inc.
发明人： Ryan Boesch , Martin Kraemer , Wei Xiong
摘要： A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.
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公开(公告)号：US11917924B2
公开(公告)日：2024-02-27
申请号：US17234792
申请日：2021-04-19
申请人： Ceremorphic, Inc.
CPC分类号： H10N50/85 , G06F7/523 , H10N50/80 , H01F10/3286 , H03K19/20
摘要： A multiplier device for binary magnetic applied fields uses Interlayer Exchange Coupling (IEC) structure where two layers of ferromagnetic material are separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. A plurality of regions on a top surface are activated with a magnetic field in a first direction for a 1 value and in an opposite direction for a 0 value, the multiplication result presented as magnetic field direction on a plurality of output ferromagnetic regions.
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公开(公告)号：US20230289287A1
公开(公告)日：2023-09-14
申请号：US18121294
申请日：2023-03-14
申请人： CEREMORPHIC, INC.
发明人： Lizy Kurian JOHN , Venkat MATTELA , Heonchul PARK
CPC分类号： G06F12/04 , G06N3/10 , G06F2212/16
摘要： A programmable address generator has an iteration variable generator for generation of an ordered set of iteration variables, which are re-ordered by an iteration variable selection fabric, which delivers the re-ordered iteration variables to one or more address generators. A configurator receives an instruction containing fields which provide configuration constants to the address generator, iteration variable selection fabric, and address generators. After configuration, the address generators provide addresses coupled to a memory. In one example of the invention, the address generators generate an input address, a coefficient address, and an output address for performing convolutional neural network inferences.
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公开(公告)号：US20220415827A1
公开(公告)日：2022-12-29
申请号：US17588767
申请日：2022-01-31
申请人： Ceremorphic, Inc.
发明人： Robert Wiser
IPC分类号： H01L23/58 , H01L23/538
摘要： A plurality of integrated circuits each have a central interconnect region which is enclosed by an inner sealring, optional intermediate sealrings, and an outer sealring. Each sealring has a sealring gap for passage of a signal trace which connects a central interconnect of a first integrated circuit to a central interconnect of a second integrated circuit. In first example of the invention, the signal trace remains on a single layer and routes through sealring layer gaps between the first and second IC. In a second example of the invention, vias are used in gaps between sealrings for the signal trace to change layers such that the sealring gaps are not on the same layer. In a third example of the invention, the vias of the second example are replaced by capacitors with plates in adjacent layers.
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公开(公告)号：US12099844B1
公开(公告)日：2024-09-24
申请号：US17827909
申请日：2022-05-30
申请人： Ceremorphic, Inc.
发明人： Somya Dashora , Kalash Bhavin Shah , Prakhar Kumar
CPC分类号： G06F9/3806 , G06F9/3844 , G06F9/3851
摘要： An exemplary branch predictor apparatus comprises a Pattern History Table (PHT) configured with a PHT allocation multiplexer/demultiplexer (PAMD) configurable to output a prediction logically selected from a portion of the PHT entries selectively allocated among a plurality of threads. The PHT entries may be allocated among a plurality of threads based on control bits read from a Control and Status Register (CSR) at system initialization. The branch predictor may govern a plurality of threads fetching instructions from an address selected from a Branch Target Buffer (BTB) entry indexed based on a per-thread Program Counter (PC) or a PHT entry indexed based on a per-thread Global History Register (GBHR). The PHT entries may be saturating binary counters. The saturating counters may be two-bit counters. An exemplary implementation may permit reduced misprediction rate, increased throughput, or reduced energy consumption resulting from increased allocation of PHT entries to more branch-intensive threads.
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