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1.发明申请公开(公告)号：US20100122038A1
公开(公告)日：2010-05-13
申请号：US12266753
申请日：2008-11-07
IPC分类号： G06F12/08
CPC分类号： G06F12/127 , G06F9/528 , G06F12/0842
摘要： Methods and apparatuses are disclosed that allow for improved speculation success in execute ahead microprocessors. In some embodiments, the method may include speculatively executing a first thread of a program code while a second thread of the program code is executing, determining if a load request is serviceable from a cache line within a cache, and in the event that the load request is serviceable from the cache line, associating a first indicator bit with the cache line. The method also may include determining whether the cache line associated with the first indicator bit has been evicted, and in the event that the cache line is evicted, allowing speculative execution of the first thread to continue.
摘要翻译： 公开了允许在执行前进微处理器中改进投机成功的方法和装置。 在一些实施例中，该方法可以包括在执行程序代码的第二线程时推测性地执行程序代码的第一线程，确定加载请求是否可从高速缓存器内的高速缓存线路服务，并且在负载 请求可从高速缓存行服务，将第一指示符位与高速缓存行相关联。 该方法还可以包括确定与第一指示符位相关联的高速缓存行是否已被驱逐，以及在高速缓存行被驱逐的情况下，允许第一线程的推测性执行继续。
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公开(公告)号：US08898401B2
公开(公告)日：2014-11-25
申请号：US12266753
申请日：2008-11-07
CPC分类号： G06F12/127 , G06F9/528 , G06F12/0842
摘要： Methods and apparatuses are disclosed that allow for improved speculation success in execute ahead microprocessors. In some embodiments, the method may include speculatively executing a first thread of a program code while a second thread of the program code is executing, determining if a load request is serviceable from a cache line within a cache, and in the event that the load request is serviceable from the cache line, associating a first indicator bit with the cache line. The method also may include determining whether the cache line associated with the first indicator bit has been evicted, and in the event that the cache line is evicted, allowing speculative execution of the first thread to continue.
摘要翻译： 公开了允许在执行前进微处理器中改进投机成功的方法和装置。 在一些实施例中，该方法可以包括在执行程序代码的第二线程时推测性地执行程序代码的第一线程，确定加载请求是否可从高速缓存器内的高速缓存线路服务，并且在负载 请求可从高速缓存行服务，将第一指示符位与高速缓存行相关联。 该方法还可以包括确定与第一指示符位相关联的高速缓存行是否已被驱逐，以及在高速缓存行被驱逐的情况下，允许第一线程的推测性执行继续。
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公开(公告)号：US4032797A
公开(公告)日：1977-06-28
申请号：US602482
申请日：1975-08-06
摘要： The analogue storage circuit comprises a nonlinear amplifier for amplifying an input voltage. The amplifier includes means for generating a sequence of predetermined voltages, each predetermined voltage being higher than the preceding one in the sequence. A plurality of voltage level responsive circuits are each connected to receive the input signal and a respective one of said predetermined voltages and are each arranged to change from a first state to a second state as the input voltage passes through a level of equality with the respective predetermined voltage in a given direction. An output circuit is provided, as well as a plurality of voltage follower circuits each having a first input connected to receive a respective one of the predetermined voltages and an output connected to the input of the output circuit. Each voltage follower circuit is arranged to be rendered operative by a respective one of the voltage level responsive circuits when the input voltage lies between the respective predetermined voltage received by that voltage level responsive circuit and the next successive predetermined voltage in the given direction. And each voltage follower circuit is arranged, when operative, to co-operate with the output circuit to maintain the output voltage substantially equal to the respective voltage at the first input of the voltage follower circuit.
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