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公开(公告)号:US08575043B2
公开(公告)日:2013-11-05
申请号:US13191430
申请日:2011-07-26
申请人: Chan-Lon Yang , Tzu-Feng Kuo , Hsin-Huei Wu , Ching-I Li , Shu-Yen Chan
发明人: Chan-Lon Yang , Tzu-Feng Kuo , Hsin-Huei Wu , Ching-I Li , Shu-Yen Chan
CPC分类号: H01L21/268 , H01L21/26586
摘要: A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an included angle.
摘要翻译: 半导体器件包括设置在半导体衬底上的多个有源区。 半导体器件的制造方法包括:通过在第一扫描方向上单独地发射第一激光,对半导体衬底进行第一退火处理,并且通过在第二扫描方向上单独地发射第二激光,对半导体衬底进行第二退火处理。 第一扫描方向和第二扫描方向具有夹角。
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公开(公告)号:US20130026543A1
公开(公告)日:2013-01-31
申请号:US13191430
申请日:2011-07-26
申请人: Chan-Lon Yang , Tzu-Feng Kuo , Hsin-Huei Wu , Ching-I Li , Shu-Yen Chan
发明人: Chan-Lon Yang , Tzu-Feng Kuo , Hsin-Huei Wu , Ching-I Li , Shu-Yen Chan
IPC分类号: H01L21/268 , H01L29/772
CPC分类号: H01L21/268 , H01L21/26586
摘要: A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an incident angle.
摘要翻译: 半导体器件包括设置在半导体衬底上的多个有源区。 半导体器件的制造方法包括:通过在第一扫描方向上单独地发射第一激光,对半导体衬底进行第一退火处理,并且通过在第二扫描方向上单独地发射第二激光,对半导体衬底进行第二退火处理。 第一扫描方向和第二扫描方向具有入射角。
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公开(公告)号:US20130052778A1
公开(公告)日:2013-02-28
申请号:US13216259
申请日:2011-08-24
申请人: Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Hsin-Huei Wu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
发明人: Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Hsin-Huei Wu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
IPC分类号: H01L21/336
CPC分类号: H01L29/66795 , H01L29/66628
摘要: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure.
摘要翻译: 半导体工艺包括以下步骤。 提供基板。 在基板上形成至少一个鳍状结构。 在基板上形成氧化层,而不形成鳍状结构。 形成栅极以覆盖氧化物层的一部分和鳍状结构的一部分。 进行蚀刻处理以蚀刻栅极旁边的鳍状结构的一部分,因此在鳍状结构中至少形成凹部。 执行外延工艺以在凹部中形成外延层,其中外延层具有六边形轮廓结构。
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公开(公告)号:US08440511B1
公开(公告)日:2013-05-14
申请号:US13298264
申请日:2011-11-16
申请人: Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Min-Ying Hsu , Hsin-Huei Wu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
发明人: Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Min-Ying Hsu , Hsin-Huei Wu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
IPC分类号: H01L21/00
CPC分类号: H01L21/306 , H01L29/66795 , H01L29/7854
摘要: A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer and a patterned hard mask sequentially formed thereon, removing the patterned hard mask, performing a thermal treatment to rounding the patterned semiconductor layer with a process temperature lower than 800° C., and sequentially forming a gate dielectric layer and a gate layer covering a portion of the patterned semiconductor layer on the semiconductor substrate.
摘要翻译: 一种用于制造多栅极晶体管器件的方法包括:提供具有图案化半导体层的半导体衬底和在其上依次形成的图案化硬掩模,去除图案化的硬掩模,进行热处理以使处理温度低于 800℃,并顺序地形成覆盖半导体衬底上的图案化半导体层的一部分的栅极电介质层和栅极层。
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公开(公告)号:US08674433B2
公开(公告)日:2014-03-18
申请号:US13216259
申请日:2011-08-24
申请人: Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Hsin-Huei Wu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
发明人: Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Hsin-Huei Wu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
IPC分类号: H01L29/66
CPC分类号: H01L29/66795 , H01L29/66628
摘要: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure.
摘要翻译: 半导体工艺包括以下步骤。 提供基板。 在基板上形成至少一个鳍状结构。 在基板上形成氧化层,而不形成鳍状结构。 形成栅极以覆盖氧化物层的一部分和鳍状结构的一部分。 进行蚀刻处理以蚀刻栅极旁边的鳍状结构的一部分,因此在鳍状结构中至少形成凹部。 执行外延工艺以在凹部中形成外延层,其中外延层具有六边形轮廓结构。
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公开(公告)号:US20130122698A1
公开(公告)日:2013-05-16
申请号:US13298264
申请日:2011-11-16
申请人: Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Min-Ying Hsu , Hsin-Huei Wu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
发明人: Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Min-Ying Hsu , Hsin-Huei Wu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
IPC分类号: H01L21/28
CPC分类号: H01L21/306 , H01L29/66795 , H01L29/7854
摘要: A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer and a patterned hard mask sequentially formed thereon, removing the patterned hard mask, performing a thermal treatment to rounding the patterned semiconductor layer with a process temperature lower than 800° C., and sequentially forming a gate dielectric layer and a gate layer covering a portion of the patterned semiconductor layer on the semiconductor substrate.
摘要翻译: 一种用于制造多栅极晶体管器件的方法包括:提供具有图案化半导体层的半导体衬底和在其上依次形成的图案化硬掩模,去除图案化的硬掩模,进行热处理以使处理温度低于 800℃,并顺序地形成覆盖半导体衬底上的图案化半导体层的一部分的栅极电介质层和栅极层。
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