公开(公告)号：US20090055202A1

公开(公告)日：2009-02-26

申请号：US11842538

申请日：2007-08-21

申请人： Chandramouli Venkatesh ,  Artem D. Yegorov ,  Ehab Sobhy ,  Xing Wu ,  Sonu Arora

发明人： Chandramouli Venkatesh ,  Artem D. Yegorov ,  Ehab Sobhy ,  Xing Wu ,  Sonu Arora

IPC分类号： G06Q99/00

CPC分类号： H04L41/0273 ,  G06Q10/06 ,  G06Q10/101 ,  G06Q2220/18

摘要： The claimed subject matter provides a system and/or a method that facilitates integrating two or more applications for secure sharing of data. A line of business (LOB) system can include a portion of metadata associated with a business application. An adapter can employ a dynamic service contract to the LOB system, wherein the service contract is a fluid contract constructed in real time from a portion of metadata selected within the LOB system. Moreover, the adapter can enable a client to access the portion of metadata selected via the service contract.

摘要翻译： 所要求保护的主题提供了一种有助于集成两个或多个应用以实现数据的安全共享的系统和/或方法。 业务线（LOB）系统可以包括与业务应用相关联的一部分元数据。 适配器可以对LOB系统采用动态服务契约，其中服务合同是从LOB系统中选择的元数据的一部分实时构建的流体契约。 此外，适配器可以使得客户端能够访问通过服务合同选择的元数据部分。

公开(公告)号：US08719335B2

公开(公告)日：2014-05-06

申请号：US11842538

申请日：2007-08-21

申请人： Chandramouli Venkatesh ,  Artem D. Yegorov ,  Ehab Sobhy ,  Xing Wu ,  Sonu Arora

发明人： Chandramouli Venkatesh ,  Artem D. Yegorov ,  Ehab Sobhy ,  Xing Wu ,  Sonu Arora

IPC分类号： G06Q99/00 ,  H04L12/24

CPC分类号： H04L41/0273 ,  G06Q10/06 ,  G06Q10/101 ,  G06Q2220/18

摘要： The claimed subject matter provides a system and/or a method that facilitates integrating two or more applications for secure sharing of data. A line of business (LOB) system can include a portion of metadata associated with a business application. An adapter can employ a dynamic service contract to the LOB system, wherein the service contract is a fluid contract constructed in real time from a portion of metadata selected within the LOB system. Moreover, the adapter can enable a client to access the portion of metadata selected via the service contract.

摘要翻译： 所要求保护的主题提供了一种有助于集成两个或多个应用以实现数据的安全共享的系统和/或方法。 业务线（LOB）系统可以包括与业务应用相关联的一部分元数据。 适配器可以对LOB系统采用动态服务契约，其中服务合同是从LOB系统中选择的元数据的一部分实时构建的流体契约。 此外，适配器可以使得客户端能够访问通过服务合同选择的元数据部分。

公开(公告)号：US10147721B1

公开(公告)日：2018-12-04

申请号：US15847996

申请日：2017-12-20

申请人： Sridhar V. Gada ,  Sonu Arora

发明人： Sridhar V. Gada ,  Sonu Arora

IPC分类号： H01L27/02 ,  H01L27/06 ,  H03H11/28 ,  H01L23/34 ,  H01L49/02 ,  H01L21/8232 ,  G11C17/16 ,  H03K5/24 ,  H01L23/525

摘要： Various on-die-precision-resistor arrays, and methods of making and calibrating the same are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip and a precision resistor array on the semiconductor chip. A replica precision resistor array is on the semiconductor chip. The replica precision resistor array is configured to mimic the resistance behavior of the precision resistor array and has a characteristic resistance that is a function of temperature. The semiconductor chip is configured to calibrate the precision resistor array using the characterized resistance as a function of temperature, a resistance offset of the precision resistor array relative to the characterized resistance as a function of temperature, and a temperature of the precision resistor array.

公开(公告)号：US20130326206A1

公开(公告)日：2013-12-05

申请号：US13547701

申请日：2012-07-12

申请人： Andrew William Lueck ,  Krishna Sai Bernucho ,  Alexander J. Branover ,  Paul Edward Kitchin ,  Ronald Perez ,  Sonu Arora

发明人： Andrew William Lueck ,  Krishna Sai Bernucho ,  Alexander J. Branover ,  Paul Edward Kitchin ,  Ronald Perez ,  Sonu Arora

IPC分类号： G06F9/00 ,  G06F1/24

CPC分类号： G06F9/4418 ,  G06F1/32

摘要： Boot configuration information is stored to a volatile memory of a processing system during a low-power state. When resuming from the low-power state, a processor device accesses configuration information for a memory controller from a non-volatile memory and restores the memory controller using the configuration information so as to permit access to the volatile memory. The processor device then configures the initial contexts one or more processor cores using the core state information maintained by the volatile memory during the low-power state and accessed via the configured memory controller, and the one or more processor cores completes the boot process by executing resume boot code maintained by the volatile memory during the low-power state and accessed via the configured memory controller, rather than accessing boot code from a non-volatile memory.

摘要翻译： 引导配置信息在低功耗状态下被存储到处理系统的易失性存储器。 当从低功率状态恢复时，处理器设备从非易失性存储器访问存储器控制器的配置信息，并使用配置信息恢复存储器控制器，以便允许访问易失性存储器。 然后，处理器设备在低功率状态期间使用由易失性存储器维护的核心状态信息来配置初始上下文一个或多个处理器核心，并经配置的存储器控​​制器访问，并且一个或多个处理器核心通过执行 在低功耗状态下恢复引导代码由易失性存储器维护并通过配置的存储器控​​制器访问，而不是从非易失性存储器访问引导代码。

公开(公告)号：US09146600B2

公开(公告)日：2015-09-29

申请号：US11870562

申请日：2007-10-11

申请人： Robert J. P. Nychka ,  Laurent Geffroy ,  Sonu Arora ,  Vipin Verma

发明人： Robert J. P. Nychka ,  Laurent Geffroy ,  Sonu Arora ,  Vipin Verma

IPC分类号： G06F1/32 ,  G11C11/4074

CPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/3275 ,  G11C11/4074

摘要： Systems and methods for discrete power control of components within a computer system are described herein. Some illustrative embodiments include a system that includes a subsystem with a plurality of components (configurable to operate at one or more power levels), a control register (coupled to the plurality of components) including a plurality of bits (each uniquely associated with a one of the plurality of components), and a power controller coupled to, and configurable to cause, the plurality of components to operate at the one or more power levels. The power controller asserts a signal transmitted to the subsystem, commanding the subsystem to transition to a first power level. A first of the plurality of components, associated with an asserted bit of the control register, operates at a second power level corresponding to a level of power consumption different from that of the first power level indicated by the power controller.

摘要翻译： 本文描述了用于计算机系统内部件的离散功率控制的系统和方法。 一些说明性实施例包括系统，其包括具有多个组件（可配置为在一个或多个功率电平下操作）的子系统，包括多个位（每个唯一地与一个位相关联的多个位组合）的控制寄存器 多个组件）以及功率控制器，其耦合到并且可配置为使多个组件在一个或多个功率水平下操作。 功率控制器断言发送到子系统的信号，命令子系统转换到第一功率电平。 与控制寄存器的断言位相关联的多个部件中的第一个在与功率控制器指示的第一功率电平的功耗水平不同的第二功率电平下工作。

公开(公告)号：US09182999B2

公开(公告)日：2015-11-10

申请号：US13547701

申请日：2012-07-12

申请人： Andrew William Lueck ,  Krishna Sai Bernucho ,  Alexander J. Branover ,  Paul Edward Kitchin ,  Ronald Perez ,  Sonu Arora

发明人： Andrew William Lueck ,  Krishna Sai Bernucho ,  Alexander J. Branover ,  Paul Edward Kitchin ,  Ronald Perez ,  Sonu Arora

IPC分类号： G06F1/32 ,  G06F9/44

CPC分类号： G06F9/4418 ,  G06F1/32

摘要： Boot configuration information is stored to a volatile memory of a processing system during a low-power state. When resuming from the low-power state, a processor device accesses configuration information for a memory controller from a non-volatile memory and restores the memory controller using the configuration information so as to permit access to the volatile memory. The processor device then configures the initial contexts one or more processor cores using the core state information maintained by the volatile memory during the low-power state and accessed via the configured memory controller, and the one or more processor cores completes the boot process by executing resume boot code maintained by the volatile memory during the low-power state and accessed via the configured memory controller, rather than accessing boot code from a non-volatile memory.

摘要翻译： 引导配置信息在低功耗状态下被存储到处理系统的易失性存储器。 当从低功率状态恢复时，处理器设备从非易失性存储器访问存储器控制器的配置信息，并使用配置信息恢复存储器控制器，以便允许访问易失性存储器。 然后，处理器设备在低功率状态期间使用由易失性存储器维护的核心状态信息来配置初始上下文一个或多个处理器核心，并经配置的存储器控​​制器访问，并且一个或多个处理器核心通过执行 在低功耗状态下恢复引导代码由易失性存储器维护并通过配置的存储器控​​制器访问，而不是从非易失性存储器访问引导代码。