公开(公告)号：US08208578B2

公开(公告)日：2012-06-26

申请号：US12820113

申请日：2010-06-21

申请人： Paul D. Franzon ,  Yongjin Choi ,  Chanyoun Won ,  Hoon Seok Kim

发明人： Paul D. Franzon ,  Yongjin Choi ,  Chanyoun Won ,  Hoon Seok Kim

IPC分类号： H04L25/34 ,  H04L25/49

CPC分类号： H04L25/0286 ,  H04L25/4917

摘要： Systems, methods, and computer readable media for fractional pre-emphasis of multi-mode interconnect are disclosed. According to one aspect, the subject matter described herein includes a method for fractional pre-emphasis of multi-mode interconnect. Multiple bits of binary data are periodically received. For each period, the multiple bits of binary data are encoded into multiple scalar values, each value representing a level of an analog signal to be output over a multi-mode interconnect system during the current period. Multiple analog signal outputs are generated corresponding to multiple scalar values, each signal output being driven to a level according to its corresponding scalar value. For each representative scalar value, a difference between the scalar value generated during the current period and the scalar value generated during the previous period is determined, and a pre-emphasis signal that is proportional to the difference is generated. Pre-emphasize each analog signal output according to the respective pre-emphasis signal, where the analog signal is pre-emphasized for a fraction of a period that is less than the entire period.

摘要翻译： 公开了用于多模互连的分数预加重的系统，方法和计算机可读介质。 根据一个方面，本文描述的主题包括用于多模互连的分数预加重的方法。 定期接收多位二进制数据。 对于每个周期，二进制数据的多个比特被编码成多个标量值，每个值表示在当前周期内通过多模式互连系统输出的模拟信号的电平。 对应于多个标量值产生多个模拟信号输出，每个信号输出根据其对应的标量值被驱动到一个电平。 对于每个代表标量值，确定在当前周期期间产生的标量值与在前一周期期间产生的标量值之间的差异，并且产生与该差异成比例的预加重信号。 根据相应的预加重信号预加强每个模拟信号输出，其中模拟信号被预先强调少于小于整个周期的周期的一小部分。

公开(公告)号：US08903010B2

公开(公告)日：2014-12-02

申请号：US13469059

申请日：2012-05-10

申请人： Chanyoun Won ,  Paul D. Franzon

发明人： Chanyoun Won ,  Paul D. Franzon

IPC分类号： H03F3/68

CPC分类号： H04L25/49 ,  H04L25/0292 ,  H04L25/03878

摘要： Methods, systems, and computer readable media for low power multimode interconnect for lossy and tightly coupled multi-channel are disclosed. According to one aspect, a system for low power multimode interconnect includes a receiver for receiving a plurality of input signals that have been encoded by a multimode encoding equation to have voltage levels according to the multimode encoding equation and for decoding the received signals according to a multimode decoding equation to produce binary data as output, wherein the receiver includes a set of frequency-compensated amplifiers for emphasizing high-frequency components of the received input signals and a set of latches for receiving amplified signals from the frequency-compensated amplifiers and for decoding the amplified signals according to the multimode decoding equation to produce binary data as output.

摘要翻译： 公开了用于有损和紧密耦合的多信道的低功率多模互连的方法，系统和计算机可读介质。 根据一个方面，一种用于低功率多模互连的系统包括：接收器，用于接收已经由多模式编码方程编码的多个输入信号，以具有根据多模式编码方程的电压电平，并且用于根据 多模解码方程以产生二进制数据作为输出，其中接收机包括用于强调接收的输入信号的高频分量的一组频率补偿放大器和一组用于接收来自频率补偿放大器的放大信号并用于解码的锁存器 根据多模解码方程的放大信号产生二进制数据作为输出。

公开(公告)号：US20130300498A1

公开(公告)日：2013-11-14

申请号：US13469059

申请日：2012-05-10

申请人： Chanyoun Won ,  Paul D. Franzon

发明人： Chanyoun Won ,  Paul D. Franzon

IPC分类号： H03F3/68

CPC分类号： H04L25/49 ,  H04L25/0292 ,  H04L25/03878

摘要： Methods, systems, and computer readable media for low power multimode interconnect for lossy and tightly coupled multi-channel are disclosed. According to one aspect, a system for low power multimode interconnect includes a receiver for receiving a plurality of input signals that have been encoded by a multimode encoding equation to have voltage levels according to the multimode encoding equation and for decoding the received signals according to a multimode decoding equation to produce binary data as output, wherein the receiver includes a set of frequency-compensated amplifiers for emphasizing high-frequency components of the received input signals and a set of latches for receiving amplified signals from the frequency-compensated amplifiers and for decoding the amplified signals according to the multimode decoding equation to produce binary data as output.

摘要翻译： 公开了用于有损和紧密耦合的多信道的低功率多模互连的方法，系统和计算机可读介质。 根据一个方面，一种用于低功率多模互连的系统包括：接收器，用于接收已经由多模式编码方程编码的多个输入信号，以具有根据多模式编码方程的电压电平，并且用于根据 多模解码方程以产生二进制数据作为输出，其中接收机包括用于强调接收的输入信号的高频分量的一组频率补偿放大器和一组用于接收来自频率补偿放大器的放大信号并用于解码的锁存器 根据多模解码方程的放大信号产生二进制数据作为输出。

公开(公告)号：US09008215B2

公开(公告)日：2015-04-14

申请号：US13538448

申请日：2012-06-29

申请人： Chanyoun Won ,  Hoon Seok Kim ,  Paul D. Franzon ,  Zhuo Yan

发明人： Chanyoun Won ,  Hoon Seok Kim ,  Paul D. Franzon ,  Zhuo Yan

IPC分类号： H04L25/49

CPC分类号： H04L25/49 ,  H04L25/14 ,  H04L25/4906 ,  H04L25/4917

摘要： Methods, systems, and computer readable media for asymmetric multimode interconnect (MMI) are disclosed. According to one aspect, a system for receiver-side asymmetric MMI includes a receiver that receives binary-encoded input signals from a multichannel interconnect, encodes the received binary-encoded signals according to a multimode encoding equation to produce multimode-encoded signals having voltage levels according to the multimode encoding equation, adjusts the timing of the multimode-encoded signals to compensate for multichannel interconnect channel delays to produce delay-adjusted multimode-encoded signals, and decodes the delay-adjusted multimode-encoded signals according to a multimode decoding equation to produce binary-encoded output signals. According to another aspect, a system for transmitter-side asymmetric MMI includes a transmitter that receives binary-encoded input signals, pre-adjusts the timing of the input signals to compensate for expected multichannel interconnect channel delays, multimode-encodes the timing-compensated binary-encoded input signals, multimode-decodes the multimode-encoded signals, and transmits the multimode-decoded signals over the multichannel interconnect.

摘要翻译： 公开了用于非对称多模互连（MMI）的方法，系统和计算机可读介质。 根据一个方面，一种用于接收机侧非对称MMI的系统包括从多通道互连接收二进制编码的输入信号的接收机，根据多模式编码方程对所接收的二进制编码信号进行编码，以产生具有电压电平的多模式编码信号 根据多模式编码方程，调整多模编码信号的定时以补偿多通道互连通道延迟以产生延迟调整的多模式编码信号，并根据多模式解码方程解码经延迟调整的多模式编码信号 产生二进制编码的输出信号。 根据另一方面，用于发射机侧非对称MMI的系统包括接收二进制编码的输入信号的发射机，预调节输入信号的定时以补偿期望的多信道互连信道延迟，对定时补偿二进制进行多模式编码 编码的输入信号，对多模式编码信号进行多模式解码，并通过多通道互连传输多模式解码信号。

公开(公告)号：US20140003549A1

公开(公告)日：2014-01-02

申请号：US13538448

申请日：2012-06-29

申请人： Chanyoun Won ,  Hoon Seok Kim ,  Paul D. Franzon ,  Zhuo Yan

发明人： Chanyoun Won ,  Hoon Seok Kim ,  Paul D. Franzon ,  Zhuo Yan

IPC分类号： H04L25/49

CPC分类号： H04L25/49 ,  H04L25/14 ,  H04L25/4906 ,  H04L25/4917

摘要： Methods, systems, and computer readable media for asymmetric multimode interconnect (MMI) are disclosed. According to one aspect, a system for receiver-side asymmetric MMI includes a receiver that receives binary-encoded input signals from a multichannel interconnect, encodes the received binary-encoded signals according to a multimode encoding equation to produce multimode-encoded signals having voltage levels according to the multimode encoding equation, adjusts the timing of the multimode-encoded signals to compensate for multichannel interconnect channel delays to produce delay-adjusted multimode-encoded signals, and decodes the delay-adjusted multimode-encoded signals according to a multimode decoding equation to produce binary-encoded output signals. According to another aspect, a system for transmitter-side asymmetric MMI includes a transmitter that receives binary-encoded input signals, pre-adjusts the timing of the input signals to compensate for expected multichannel interconnect channel delays, multimode-encodes the timing-compensated binary-encoded input signals, multimode-decodes the multimode-encoded signals, and transmits the multimode-decoded signals over the multichannel interconnect.

摘要翻译： 公开了用于非对称多模互连（MMI）的方法，系统和计算机可读介质。 根据一个方面，一种用于接收机侧非对称MMI的系统包括从多通道互连接收二进制编码的输入信号的接收机，根据多模式编码方程对所接收的二进制编码信号进行编码，以产生具有电压电平的多模式编码信号 根据多模式编码方程，调整多模编码信号的定时以补偿多通道互连通道延迟以产生延迟调整的多模式编码信号，并根据多模式解码方程解码经延迟调整的多模式编码信号 产生二进制编码的输出信号。 根据另一方面，用于发射机侧非对称MMI的系统包括接收二进制编码的输入信号的发射机，预调节输入信号的定时以补偿期望的多信道互连信道延迟，对定时补偿二进制进行多模式编码 编码的输入信号，对多模式编码信号进行多模式解码，并通过多通道互连传输多模式解码信号。

公开(公告)号：US20110310992A1

公开(公告)日：2011-12-22

申请号：US12820113

申请日：2010-06-21

申请人： Paul D. Franzon ,  Yongjin Choi ,  Chanyoun Won ,  Hoon Seok Kim

发明人： Paul D. Franzon ,  Yongjin Choi ,  Chanyoun Won ,  Hoon Seok Kim

IPC分类号： H04L25/34

CPC分类号： H04L25/0286 ,  H04L25/4917

摘要： Systems, methods, and computer readable media for fractional pre-emphasis of multi-mode interconnect are disclosed. According to one aspect, the subject matter described herein includes a method for fractional pre-emphasis of multi-mode interconnect. Multiple bits of binary data are periodically received. For each period, the multiple bits of binary data are encoded into multiple scalar values, each value representing a level of an analog signal to be output over a multi-mode interconnect system during the current period. Multiple analog signal outputs are generated corresponding to multiple scalar values, each signal output being driven to a level according to its corresponding scalar value. For each representative scalar value, a difference between the scalar value generated during the current period and the scalar value generated during the previous period is determined, and a pre-emphasis signal that is proportional to the difference is generated. Pre-emphasize each analog signal output according to the respective pre-emphasis signal, where the analog signal is pre-emphasized for a fraction of a period that is less than the entire period.

摘要翻译： 公开了用于多模互连的分数预加重的系统，方法和计算机可读介质。 根据一个方面，本文描述的主题包括用于多模互连的分数预加重的方法。 定期接收多位二进制数据。 对于每个周期，二进制数据的多个比特被编码成多个标量值，每个值表示在当前周期内通过多模式互连系统输出的模拟信号的电平。 对应于多个标量值产生多个模拟信号输出，每个信号输出根据其对应的标量值被驱动到一个电平。 对于每个代表标量值，确定在当前周期期间产生的标量值与在前一周期期间产生的标量值之间的差异，并且产生与该差异成比例的预加重信号。 根据相应的预加重信号预加强每个模拟信号输出，其中模拟信号被预先强调少于小于整个周期的周期的一小部分。

公开(公告)号：US09077245B2

公开(公告)日：2015-07-07

申请号：US13615412

申请日：2012-09-13

申请人： Paul D. Franzon ,  Peter Gadfort ,  Joshua Chris Ledford

发明人： Paul D. Franzon ,  Peter Gadfort ,  Joshua Chris Ledford

IPC分类号： H03K19/094 ,  H03K19/20 ,  H02M7/217 ,  H02M7/219

CPC分类号： H02M7/217 ,  H02M2007/2195 ,  H03K19/094 ,  Y02B70/1408

摘要： AC powered logic circuits and systems including same are disclosed. According to one aspect, a system including a logic circuit powered using an alternating current (AC) power source includes at least one supply transistor connected to receive voltages of opposite phases from an AC power source such that the at least one supply transistor is strongly on during a first phase of the voltage of the AC power source and is strongly off during a second phase opposite the first phase of the voltage of the AC power source and at least one logic circuit connected to be powered by the AC power source through the at least one supply transistor and producing an output at an output terminal responsive to an input received at an input terminal.

摘要翻译： 公开了交流供电的逻辑电路及包括它们的系统。 根据一个方面，一种包括使用交流（AC）电源供电的逻辑电路的系统包括至少一个电源晶体管，其被连接以接收来自AC电源的相反相位的电压，使得至少一个电源晶体管强烈地接通 在交流电源的电压的第一阶段期间，并且在与交流电源的电压的第一相位相反的第二阶段期间强制关闭，以及至少一个逻辑电路，所述至少一个逻辑电路通过所述交流电源由所述交流电源供电 至少一个电源晶体管，并响应于在输入端接收的输入而在输出端产生输出。

公开(公告)号：US09762434B2

公开(公告)日：2017-09-12

申请号：US14236572

申请日：2012-07-20

申请人： Paul D. Franzon ,  John Wilson

发明人： Paul D. Franzon ,  John Wilson

IPC分类号： H04L12/24 ,  G06F11/20 ,  H04L1/22 ,  H03L7/18 ,  H03L7/23 ,  H04L1/00

CPC分类号： H04L41/0686 ,  G06F11/2007 ,  H03L7/18 ,  H03L7/23 ,  H04L1/0002 ,  H04L1/22 ,  H04L41/0659 ,  H04L41/0668

摘要： A circuit is provided to facilitate temporal redundancy for inter-chip communication. When an inter-chip communication channel fails, data bits associated with the faulty channel are steered to a non-faulty channel and transmitted via the non-faulty channel together with data bits associated with the non-faulty channel at an increased data rate.

公开(公告)号：US09252501B2

公开(公告)日：2016-02-02

申请号：US13481928

申请日：2012-05-28

申请人： Paul D. Franzon ,  Peter Gadfort ,  Wallace Shepherd Pitts

发明人： Paul D. Franzon ,  Peter Gadfort ,  Wallace Shepherd Pitts

IPC分类号： H01Q21/20 ,  H01Q1/38 ,  H01Q7/00 ,  H01Q21/24

CPC分类号： H01Q21/205 ,  H01Q1/38 ,  H01Q7/00 ,  H01Q21/24 ,  Y10T29/49016

摘要： Millimeter scale three dimensional antenna structures and methods for fabricating such structures are disclosed. According to one method, a first substantially planar die having a first antenna structure is placed on a first surface. A second substantially planar die having at least one conductive element is placed on a second surface that forms an oblique angle with the first surface. The first and second dies are mechanically coupled to each other such that the first die and the first antenna structure extend at the oblique angle to the second die.

摘要翻译： 公开了毫米级三维天线结构及其制造方法。 根据一种方法，具有第一天线结构的第一基本上平面的管芯被放置在第一表面上。 具有至少一个导电元件的第二基本上平面的模具放置在与第一表面形成倾斜角的第二表面上。 第一和第二管芯彼此机械耦合，使得第一管芯和第一天线结构以与第二管芯的倾斜角度延伸。

公开(公告)号：US20130069709A1

公开(公告)日：2013-03-21

申请号：US13615412

申请日：2012-09-13

申请人： Paul D. Franzon ,  Peter Gadfort ,  Joshua Chris Ledford

发明人： Paul D. Franzon ,  Peter Gadfort ,  Joshua Chris Ledford

IPC分类号： H02M7/217 ,  H03L5/00 ,  H01F38/14 ,  H02M7/00

CPC分类号： H02M7/217 ,  H02M2007/2195 ,  H03K19/094 ,  Y02B70/1408

摘要： AC powered logic circuits and systems including same are disclosed. According to one aspect, a system including a logic circuit powered using an alternating current (AC) power source includes at least one supply transistor connected to receive voltages of opposite phases from an AC power source such that the at least one supply transistor is strongly on during a first phase of the voltage of the AC power source and is strongly off during a second phase opposite the first phase of the voltage of the AC power source and at least one logic circuit connected to be powered by the AC power source through the at least one supply transistor and producing an output at an output terminal responsive to an input received at an input terminal.

摘要翻译： 公开了交流供电的逻辑电路及包括它们的系统。 根据一个方面，一种包括使用交流（AC）电源供电的逻辑电路的系统包括至少一个电源晶体管，其被连接以接收来自AC电源的相反相位的电压，使得至少一个电源晶体管强烈地接通 在交流电源的电压的第一阶段期间，并且在与交流电源的电压的第一相位相反的第二阶段期间强制关闭，以及至少一个逻辑电路，所述至少一个逻辑电路通过交流电源由交流电源供电 至少一个电源晶体管，并响应于在输入端接收的输入而在输出端产生输出。