公开(公告)号：US07023263B2

公开(公告)日：2006-04-04

申请号：US10709101

申请日：2004-04-14

申请人： Chia-Jun Chang ,  Chao-Cheng Lee

发明人： Chia-Jun Chang ,  Chao-Cheng Lee

IPC分类号： H04B1/10

CPC分类号： H03H11/245 ,  H03H11/126

摘要： A low pass filter includes a differential amplifier including a positive input end, a negative input end, a positive output end, and a negative output end. A first resistive device is coupled between the negative input end and a first node. A second resistive device is coupled between the positive input end and the first node. A third resistive device substantially the same as the second resistive device is coupled between the negative input end and a second node. A fourth resistive device substantially the same as the first resistive device is coupled between the positive input end and the second node. A first capacitive device is coupled between the negative input end and the positive output end. Finally, a second capacitive device substantially the same as the first capacitive device is coupled between the positive input end and the negative output end.

摘要翻译： 低通滤波器包括具有正输入端，负输入端，正输出端和负输出端的差分放大器。 第一电阻器件耦合在负输入端和第一节点之间。 第二电阻器件耦合在正输入端和第一节点之间。 与第二电阻装置基本相同的第三电阻装置耦合在负输入端和第二节点之间。 与第一电阻器件基本相同的第四电阻器件耦合在正输入端和第二节点之间。 第一电容器件耦合在负输入端和正输出端之间。 最后，与第一电容性装置基本相同的第二电容性装置耦合在正输入端和负输出端之间。

公开(公告)号：US08095101B2

公开(公告)日：2012-01-10

申请号：US12060849

申请日：2008-04-01

申请人： Pei-Ju Chiu ,  Chia-Jun Chang ,  Chao-Cheng Lee

发明人： Pei-Ju Chiu ,  Chia-Jun Chang ,  Chao-Cheng Lee

IPC分类号： H04B1/06 ,  H04B7/00 ,  H04B1/28

CPC分类号： H03F3/189 ,  H03F2200/271 ,  H03F2200/375 ,  H04B1/30

摘要： A receiving device includes a mixer, an AC coupling circuit, a post-stage circuit, and a DC offset calibration circuit. The mixer is utilized for mixing an input signal with a local oscillating (LO) signal from an oscillator to generate a converted signal. The AC coupling circuit is coupled to the mixer and utilized for reducing at least one portion of DC offset of the converted signal to generate a filtered signal. The post-stage circuit is coupled to the AC coupling circuit and utilized for processing the filtered signal to generate an output signal. The DC offset calibration circuit is coupled to the post-stage circuit and utilized for providing at least a compensation current for the post-stage circuit to reduce DC offset of the output signal.

摘要翻译： 接收装置包括混频器，AC耦合电路，后级电路和DC偏移校准电路。 混频器用于将输入信号与来自振荡器的本地振荡（LO）信号混合以产生转换的信号。 AC耦合电路耦合到混频器并用于减少转换信号的DC偏移的至少一部分以产生滤波信号。 后级电路耦合到AC耦合电路，用于处理滤波后的信号以产生输出信号。 DC偏移校准电路耦合到后级电路，并用于为后级电路提供至少一个补偿电流，以减少输出信号的DC偏移。

公开(公告)号：US07106131B2

公开(公告)日：2006-09-12

申请号：US10707803

申请日：2004-01-13

申请人： Chao-Cheng Lee ,  Chia-Jun Chang

发明人： Chao-Cheng Lee ,  Chia-Jun Chang

IPC分类号： H03F3/45

CPC分类号： H03F3/005 ,  H03F3/45475

摘要： An amplifying circuit includes a differential amplifier having a positive input end, a negative input end, a positive output end, and a negative output end; a first input impedance coupled between the negative input end and a first input signal; a second input impedance coupled between the positive input end and the first input signal; a third input impedance coupled between the negative input end and a second input signal; a fourth input impedance coupled between the positive input end and the second input signal; a first output impedance coupled between the negative input end and the positive output end; a second output impedance coupled between the negative input end and the negative output end; a third output impedance coupled between the positive input end and the positive output end; and a fourth output impedance coupled between the positive input end and the negative output end.

摘要翻译： 放大电路包括具有正输入端，负输入端，正输出端和负输出端的差分放大器; 耦合在所述负输入端和第一输入信号之间的第一输入阻抗; 耦合在正输入端和第一输入信号之间的第二输入阻抗; 耦合在所述负输入端和第二输入信号之间的第三输入阻抗; 耦合在正输入端和第二输入信号之间的第四输入阻抗; 耦合在负输入端和正输出端之间的第一输出阻抗; 耦合在负输入端和负输出端之间的第二输出阻抗; 耦合在正输入端和正输出端之间的第三输出阻抗; 以及耦合在正输入端和负输出端之间的第四输出阻抗。

公开(公告)号：US20050068095A1

公开(公告)日：2005-03-31

申请号：US10709101

申请日：2004-04-14

申请人： Chia-Jun Chang ,  Chao-Cheng Lee

发明人： Chia-Jun Chang ,  Chao-Cheng Lee

IPC分类号： H02H3/20 ,  H03F3/191 ,  H03H11/12 ,  H03H11/24 ,  H03K5/00

CPC分类号： H03H11/245 ,  H03H11/126

摘要： A low pass filter includes a differential amplifier including a positive input end, a negative input end, a positive output end, and a negative output end. A first resistive device is coupled between the negative input end and a first node. A second resistive device is coupled between the positive input end and the first node. A third resistive device substantially the same as the second resistive device is coupled between the negative input end and a second node. A fourth resistive device substantially the same as the first resistive device is coupled between the positive input end and the second node. A first capacitive device is coupled between the negative input end and the positive output end. Finally, a second capacitive device substantially the same as the first capacitive device is coupled between the positive input end and the negative output end.

摘要翻译： 低通滤波器包括具有正输入端，负输入端，正输出端和负输出端的差分放大器。 第一电阻器件耦合在负输入端和第一节点之间。 第二电阻器件耦合在正输入端和第一节点之间。 与第二电阻装置基本相同的第三电阻装置耦合在负输入端和第二节点之间。 与第一电阻器件基本相同的第四电阻器件耦合在正输入端和第二节点之间。 第一电容器件耦合在负输入端和正输出端之间。 最后，与第一电容性装置基本相同的第二电容性装置耦合在正输入端和负输出端之间。

公开(公告)号：US20080238538A1

公开(公告)日：2008-10-02

申请号：US12060849

申请日：2008-04-01

申请人： Pei-Ju Chiu ,  Chia-Jun Chang ,  Chao-Cheng Lee

发明人： Pei-Ju Chiu ,  Chia-Jun Chang ,  Chao-Cheng Lee

IPC分类号： H03F1/50

CPC分类号： H03F3/189 ,  H03F2200/271 ,  H03F2200/375 ,  H04B1/30

摘要： A receiving device includes a mixer, an AC coupling circuit, a post-stage circuit, and a DC offset calibration circuit. The mixer is utilized for mixing an input signal with a local oscillating (LO) signal from an oscillator to generate a converted signal. The AC coupling circuit is coupled to the mixer and utilized for reducing at least one portion of DC offset of the converted signal to generate a filtered signal. The post-stage circuit is coupled to the AC coupling circuit and utilized for processing the filtered signal to generate an output signal. The DC offset calibration circuit is coupled to the post-stage circuit and utilized for providing at least a compensation current for the post-stage circuit to reduce DC offset of the output signal.

摘要翻译： 接收装置包括混频器，AC耦合电路，后级电路和DC偏移校准电路。 混频器用于将输入信号与来自振荡器的本地振荡（LO）信号混合以产生转换的信号。 AC耦合电路耦合到混频器并用于减少转换信号的DC偏移的至少一部分以产生滤波信号。 后级电路耦合到AC耦合电路，用于处理滤波后的信号以产生输出信号。 DC偏移校准电路耦合到后级电路，并用于为后级电路提供至少一个补偿电流，以减少输出信号的DC偏移。

公开(公告)号：US20050151576A1

公开(公告)日：2005-07-14

申请号：US10907032

申请日：2005-03-17

申请人： Chao-Cheng Lee ,  Chia-Jun Chang

发明人： Chao-Cheng Lee ,  Chia-Jun Chang

IPC分类号： H02H3/20 ,  H03H11/12 ,  H03H11/24 ,  H03K5/00

CPC分类号： H03H11/245

摘要： An impedance apparatus for providing an equivalent impedance between a first node and a second node. The impedance apparatus includes a first impedance device having a first impedance value; a second impedance device having a second impedance value; a first switch element coupled to the first impedance device; a second switch element coupled to the second impedance device; and a controller coupled to the first switch element and the second switch element; wherein the first switch element is controlled by the controller to be periodically turned on and off, and the second switch element is controlled by the controller to be periodically turned on and off.

摘要翻译： 一种用于在第一节点和第二节点之间提供等效阻抗的阻抗装置。 阻抗装置包括具有第一阻抗值的第一阻抗装置; 具有第二阻抗值的第二阻抗器件; 耦合到所述第一阻抗装置的第一开关元件; 耦合到所述第二阻抗装置的第二开关元件; 以及耦合到所述第一开关元件和所述第二开关元件的控制器; 其中所述第一开关元件由所述控制器控制以周期性地接通和断开，并且所述第二开关元件由所述控制器控制以周期性地接通和断开。

公开(公告)号：US07015730B2

公开(公告)日：2006-03-21

申请号：US10851175

申请日：2004-05-24

申请人： Chia-Jun Chang ,  Chao-Cheng Lee

发明人： Chia-Jun Chang ,  Chao-Cheng Lee

IPC分类号： G11C27/02

CPC分类号： H03M1/0663 ,  H03M1/1245

摘要： The invention is to provide a receiving end architecture comprising a variable gain amplifier, for outputting a pair of differential signals comprising a first signal and a second signal via a first and a second outputs respectively according to the receiving signal through adjusting the amplitude of the receiving signal; a mix-type sample-and-hold circuit for outputting a first sampled signal via a first end and a second sampled signal via a second end and then outputting the second sampled signal via the first end and the first sampled signal via the second end through performing sample-and-hold on the pair of differential signals; and an analog/digital converter coupled to the mix-type sample-and-hold circuit for generating a digital signal according to the first and the second sampled signals.

摘要翻译： 本发明是提供一种包括可变增益放大器的接收端架构，用于经由第一和第二输出分别经由第一和第二输出通过调整接收的振幅来输出包括第一和第二输出的一对差分信号 信号; 混合型采样和保持电路，用于经由第一端输出第一采样信号和经由第二端输出第二采样信号，然后经由第一端和第一采样信号经由第二端经由第二端输出第二采样信号 对差分信号对进行采样和保持; 以及耦合到所述混合型取样和保持电路的模拟/数字转换器，用于根据所述第一和第二采样信号产生数字信号。

公开(公告)号：US08416025B2

公开(公告)日：2013-04-09

申请号：US12759704

申请日：2010-04-14

申请人： Chia-Liang Lin ,  Chao-Cheng Lee

发明人： Chia-Liang Lin ,  Chao-Cheng Lee

IPC分类号： H03L7/087 ,  H03L7/07 ,  H03L7/093 ,  H03L7/22

CPC分类号： H03L7/0805 ,  H03L7/22

摘要： A reference assisted control system and method thereof are disclosed. The method comprises: receiving a first input signal and a second control signal; generating a first intermediate signal in accordance with a difference between the first input signal and the first output signal; filtering the second control signal to generate a second intermediate signal; performing a weighted sum of the first intermediate signal and the second intermediate signal to generate the control signal; and outputting the first output signal in accordance with the control signal.

摘要翻译： 公开了一种参考辅助控制系统及其方法。 该方法包括：接收第一输入信号和第二控制信号; 根据第一输入信号和第一输出信号之间的差产生第一中间信号; 对第二控制信号进行滤波以产生第二中间信号; 执行第一中间信号和第二中间信号的加权和以产生控制信号; 并根据控制信号输出第一输出信号。

公开(公告)号：US20120235763A1

公开(公告)日：2012-09-20

申请号：US13048877

申请日：2011-03-16

申请人： Chao-Cheng Lee ,  Tzu-Chien Tzeng

发明人： Chao-Cheng Lee ,  Tzu-Chien Tzeng

IPC分类号： H04B3/04

CPC分类号： H04B3/04 ,  H04L25/03885

摘要： An equalizer and a related equalizing method for equalizing signal reflection caused by a stub at a transmitting end are provided. The equalizer includes a summing device and a delay device. The summing device is utilized for adding a feedback delay signal to the input signal to generate the equalized signal. The delay device is coupled to the summing device, and utilized for delaying the equalized signal to generate the feedback delay signal. Wherein the delay device has a variable delay time and the variable delay time is a non-integer multiple of a bit time of the input signal.

摘要翻译： 提供了均衡器和相关均衡方法，用于均衡由发送端的短截线引起的信号反射。 均衡器包括求和装置和延迟装置。 求和装置用于将反馈延迟信号添加到输入信号以产生均衡信号。 延迟装置耦合到求和装置，用于延迟均衡信号以产生反馈延迟信号。 其中延迟装置具有可变的延迟时间，并且可变延迟时间是输入信号的位时间的非整数倍。

公开(公告)号：US20110089982A1

公开(公告)日：2011-04-21

申请号：US12580556

申请日：2009-10-16

申请人： Hong-Yean Hsieh ,  Chao-Cheng Lee

发明人： Hong-Yean Hsieh ,  Chao-Cheng Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/113 ,  H03L7/091 ,  H03L7/099 ,  H03L2207/50

摘要： An apparatus and a method for achieving lock-in of a phase-locked loop (PLL) are disclosed. The PLL receives a reference clock and generates an output clock according to the reference clock. The method comprises: adjusting an oscillation frequency of a controlled oscillator of the PLL close to a desired frequency by counting the number of rising edges of a first clock in a number of a second clock cycles; aligning a rising edge of a third clock and a rising edge of a fourth clock by temporarily changing the oscillation frequency of the digitally controlled oscillator; and locking the phases of the third and fourth clocks by a phase detector of the PLL, wherein the first and the third clocks correspond to the output clock and the second and fourth clocks correspond to the reference clock.

摘要翻译： 公开了一种用于实现锁相环（PLL）锁定的装置和方法。 PLL接收参考时钟，并根据参考时钟产生输出时钟。 该方法包括：通过以第二时钟周期的数量计数第一时钟的上升沿的数量来调节PLL的受控振荡器的振荡频率接近期望的频率; 通过临时改变数字控制振荡器的振荡频率，对准第三时钟的上升沿和第四时钟的上升沿; 以及通过PLL的相位检测器锁定第三和第四时钟的相位，其中第一和第三时钟对应于输出时钟，第二和第四时钟对应于参考时钟。