公开(公告)号：US20100251076A1

公开(公告)日：2010-09-30

申请号：US12646936

申请日：2009-12-23

申请人： Chao-Yi Wu ,  Li-Lien Lin ,  Chien-Chung Wu ,  Ching-Hao Yu

发明人： Chao-Yi Wu ,  Li-Lien Lin ,  Chien-Chung Wu ,  Ching-Hao Yu

IPC分类号： H03M13/45 ,  G06F11/10

CPC分类号： H03M13/152 ,  G06F11/1068 ,  H03M13/6516

摘要： An exemplary storage controller for controlling data access of a storage device includes a control circuit and a soft decoder. The control circuit is utilized for reading data from the storage device to obtain readout data. The soft decoder is coupled to the control circuit, and utilized for performing a soft decoding operation upon the readout data to generate decoded data. The soft decoder may be a low density parity check (LDPC) decoder, a block turbo code (BTC) decoder, or a convolutional turbo code (CTC) decoder. The storage device may be a flash memory device.

摘要翻译： 用于控制存储设备的数据访问的示例性存储控制器包括控制电路和软解码器。 控制电路用于从存储装置读取数据以获得读出数据。 软解码器耦合到控制电路，用于对读出的数据执行软解码操作以产生解码的数据。 软解码器可以是低密度奇偶校验（LDPC）解码器，块turbo码（BTC）解码器或卷积turbo码（CTC）解码器。 存储设备可以是闪存设备。

公开(公告)号：US08510631B2

公开(公告)日：2013-08-13

申请号：US12624553

申请日：2009-11-24

申请人： Chien-Chung Wu ,  Ching-Hao Yu ,  Li-Lien Lin ,  Chao-Yi Wu

发明人： Chien-Chung Wu ,  Ching-Hao Yu ,  Li-Lien Lin ,  Chao-Yi Wu

IPC分类号： G06F11/00

CPC分类号： G06F11/1044

摘要： A multi-channel memory apparatus is provided. The multi-channel memory apparatus includes a host interface, storage channels, an error correcting module, and a multiple memory access module. The host interface is arranged to receive and transmit data from and to a host device. Each storage channel is coupled to a memory device for storing the data. The error correcting module is shared by the storage channels, includes an error correction code engine and a data buffer, and is arranged to perform error correction code encoding on the data to be stored into the memory devices and perform error correction code decoding on the data read out from the memory devices. The multiple memory access module is coupled between the storage channels and the error correcting module and arranged to perform multiple access control of the storage channels for the error correcting module.

摘要翻译： 提供了一种多通道存储装置。 多通道存储装置包括主机接口，存储通道，纠错模块和多存储器访问模块。 主机接口被布置成从主机设备接收和发送数据。 每个存储通道耦合到用于存储数据的存储器件。 纠错模块由存储通道共享，包括纠错码引擎和数据缓冲器，并且被配置为对要存储到存储器件中的数据执行纠错码编码，并对数据执行纠错码解码 从内存设备中读出。 多存储器访问模块耦合在存储通道和纠错模块之间，并被布置为对错误校正模块执行存储通道的多次访问控制。

公开(公告)号：US20110126079A1

公开(公告)日：2011-05-26

申请号：US12624553

申请日：2009-11-24

申请人： Chien-Chung Wu ,  Ching-Hao Yu ,  Li-Lien Lin ,  Chao-Yi Wu

发明人： Chien-Chung Wu ,  Ching-Hao Yu ,  Li-Lien Lin ,  Chao-Yi Wu

IPC分类号： G11C29/00 ,  G06F11/00

CPC分类号： G06F11/1044

摘要： A multi-channel memory apparatus is provided. The multi-channel memory apparatus includes a host interface, storage channels, an error correcting module, and a multiple memory access module. The host interface is arranged to receive and transmit data from and to a host device. Each storage channel is coupled to a memory device for storing the data. The error correcting module is shared by the storage channels, includes an error correction code engine and a data buffer, and is arranged to perform error correction code encoding on the data to be stored into the memory devices and perform error correction code decoding on the data read out from the memory devices. The multiple memory access module is coupled between the storage channels and the error correcting module and arranged to perform multiple access control of the storage channels for the error correcting module.

摘要翻译： 提供了一种多通道存储装置。 多通道存储装置包括主机接口，存储通道，纠错模块和多存储器访问模块。 主机接口被布置成从主机设备接收和发送数据。 每个存储通道耦合到用于存储数据的存储器件。 纠错模块由存储通道共享，包括纠错码引擎和数据缓冲器，并且被配置为对要存储到存储器件中的数据执行纠错码编码，并对数据执行纠错码解码 从内存设备中读出。 多存储器访问模块耦合在存储通道和纠错模块之间，并被布置为对错误校正模块执行存储通道的多次访问控制。

公开(公告)号：US08418021B2

公开(公告)日：2013-04-09

申请号：US12645490

申请日：2009-12-23

申请人： Li-Lien Lin ,  Chao-Yi Wu ,  Chien-Chung Wu ,  Li-Chun Tu

发明人： Li-Lien Lin ,  Chao-Yi Wu ,  Chien-Chung Wu ,  Li-Chun Tu

IPC分类号： G06F11/00

CPC分类号： H03M13/152 ,  G06F11/1068 ,  H03M13/6516

摘要： One exemplary storage controller of controlling data access of a storage device includes an encoding circuit and a control circuit. The encoding circuit is programmable to support a plurality of different finite fields, and implemented for generating encoded data according to an adjustable finite field setting. The control circuit is implemented for controlling the adjustable finite field setting of the encoding circuit and recording data into the storage device according to the encoded data. Another exemplary storage controller of controlling data access of a storage device includes a decoding circuit and a control circuit. The decoding circuit is programmable to support a plurality of different finite fields, and implemented for generating decoded data according to an adjustable finite field setting. The control circuit is implemented for reading data from the storage device to obtain readout data and controlling the adjustable finite field setting of the decoding circuit.

摘要翻译： 用于控制存储设备的数据访问的一个示例性存储控制器包括编码电路和控制电路。 编码电路是可编程的，以支持多个不同的有限域，并且被实现用于根据可调节的有限域设置产生编码数据。 实施控制电路，用于控制编码电路的可调节有限域设置，并根据编码数据将数据记录到存储设备中。 用于控制存储设备的数据访问的另一示例性存储控制器包括解码电路和控制电路。 解码电路是可编程的以支持多个不同的有限域，并且被实现用于根据可调整的有限域设置产生解码数据。 控制电路实现用于从存储装置读取数据以获得读出数据并控制解码电路的可调节有限域设置。

公开(公告)号：US20100251068A1

公开(公告)日：2010-09-30

申请号：US12645490

申请日：2009-12-23

申请人： Li-Lien Lin ,  Chao-Yi Wu ,  Chien-Chung Wu ,  Li-Chun Tu

发明人： Li-Lien Lin ,  Chao-Yi Wu ,  Chien-Chung Wu ,  Li-Chun Tu

IPC分类号： H03M13/05 ,  G06F11/10 ,  H03M13/29

CPC分类号： H03M13/152 ,  G06F11/1068 ,  H03M13/6516

摘要： One exemplary storage controller of controlling data access of a storage device includes an encoding circuit and a control circuit. The encoding circuit is programmable to support a plurality of different finite fields, and implemented for generating encoded data according to an adjustable finite field setting. The control circuit is implemented for controlling the adjustable finite field setting of the encoding circuit and recording data into the storage device according to the encoded data. Another exemplary storage controller of controlling data access of a storage device includes a decoding circuit and a control circuit. The decoding circuit is programmable to support a plurality of different finite fields, and implemented for generating decoded data according to an adjustable finite field setting. The control circuit is implemented for reading data from the storage device to obtain readout data and controlling the adjustable finite field setting of the decoding circuit.

摘要翻译： 用于控制存储设备的数据访问的一个示例性存储控制器包括编码电路和控制电路。 编码电路是可编程的，以支持多个不同的有限域，并且被实现用于根据可调节的有限域设置产生编码数据。 实施控制电路，用于控制编码电路的可调节有限域设置，并根据编码数据将数据记录到存储设备中。 用于控制存储设备的数据访问的另一示例性存储控制器包括解码电路和控制电路。 解码电路是可编程的以支持多个不同的有限域，并且被实现用于根据可调整的有限域设置产生解码数据。 控制电路实现用于从存储装置读取数据以获得读出数据并控制解码电路的可调节有限域设置。

公开(公告)号：US07458847B1

公开(公告)日：2008-12-02

申请号：US11802869

申请日：2007-05-25

申请人： Yuan-Liang Hsu ,  Lien-Hsun Ho ,  Tung-Yuan Chen ,  Chao-Yi Wu

发明人： Yuan-Liang Hsu ,  Lien-Hsun Ho ,  Tung-Yuan Chen ,  Chao-Yi Wu

IPC分类号： H01R13/60

CPC分类号： H01R29/00 ,  H01R13/629

摘要： A connection assembly for offsetting tilting caused by weight difference between two objects includes a first male connector, a second male connector linearly misaligned with the first male connector, a first female connector and a second female connector linearly misaligned with the first female connector. Both the first and second male connectors are formed on a first object and both the first and second female connectors are formed on a second object. Due to the misaligned relationship, weight of the combination between the first object and the second object is redistributed to avoid tilting.

摘要翻译： 用于抵消由两个物体之间的重量差引起的倾斜的连接组件包括第一阳连接器，与第一阳连接器线性不对准的第二阳连接器，与第一阴连接器线性不对准的第一阴连接器和第二阴连接器。 第一和第二阳连接器都形成在第一物体上，并且第一和第二阴连接器都形成在第二物体上。 由于不对齐的关系，重新分配第一物体和第二物体之间的组合的重量以避免倾斜。

公开(公告)号：US20090323487A1

公开(公告)日：2009-12-31

申请号：US12413982

申请日：2009-03-30

申请人： Hsin-Cheng Chen ,  Chao-Yi Wu ,  Chia-Hung Lee ,  Yao-Chun Fang

发明人： Hsin-Cheng Chen ,  Chao-Yi Wu ,  Chia-Hung Lee ,  Yao-Chun Fang

IPC分类号： G11B20/00

CPC分类号： G11B20/1879 ,  G11B20/1217 ,  G11B2020/1221 ,  G11B2020/1297 ,  G11B2220/2537

摘要： The invention provides a method for data recording of an optical disk drive. First, raw data is encoded to obtain a plurality of recording units of encoded data to be stored in a memory. The encoded data stored in the memory is then recorded to an optical disk. A predetermined number of recording units of the encoded data is then reserved in the memory as reserved data without being recorded onto the optical disk. The recorded data read from the optical disk is then compared to the corresponding encoded data stored in the memory to verify correctness of the recorded data. The reserved data is then recorded to the optical disk after correctness verification of the recorded data is completed. Finally, the aforementioned steps are repeated until there is no more raw data left as a source for encoding.

摘要翻译： 本发明提供一种光盘驱动器的数据记录方法。 首先，原始数据被编码以获得要存储在存储器中的多个编码数据的记录单元。 然后将存储在存储器中的编码数据记录到光盘。 然后将编码数据的预定数量的记录单元作为保留数据保留在存储器中，而不被记录在光盘上。 然后将从光盘读取的记录数据与存储在存储器中的相应编码数据进行比较，以验证记录数据的正确性。 然后，在记录数据的正确性验证完成之后，保留的数据被记录到光盘。 最后，重复上述步骤，直到不再有原始数据作为编码源。

公开(公告)号：US20080293273A1

公开(公告)日：2008-11-27

申请号：US11802869

申请日：2007-05-25

申请人： Yuan-Liang Hsu ,  Lien-Hsun Ho ,  Tung-Yuan Chen ,  Chao-Yi Wu

发明人： Yuan-Liang Hsu ,  Lien-Hsun Ho ,  Tung-Yuan Chen ,  Chao-Yi Wu

IPC分类号： H01R13/62

CPC分类号： H01R29/00 ,  H01R13/629

摘要： A connection assembly for offsetting tilting caused by weight difference between two objects includes a first male connector, a second male connector linearly misaligned with the first male connector, a first female connector and a second female connector linearly misaligned with the first female connector. Both the first and second male connectors are formed on a first object and both the first and second female connectors are formed on a second object. Due to the misaligned relationship, weight of the combination between the first object and the second object is redistributed to avoid tilting.

摘要翻译： 用于抵消由两个物体之间的重量差引起的倾斜的连接组件包括第一阳连接器，与第一阳连接器线性不对准的第二阳连接器，与第一阴连接器线性不对准的第一阴连接器和第二阴连接器。 第一和第二阳连接器都形成在第一物体上，并且第一和第二阴连接器都形成在第二物体上。 由于不对齐的关系，重新分配第一物体和第二物体之间的组合的重量以避免倾斜。

公开(公告)号：US20080064249A1

公开(公告)日：2008-03-13

申请号：US11518348

申请日：2006-09-08

申请人： Lien-Hsun Ho ,  Yuan-Liang Hsu ,  Shou-Ting Yeh ,  Chuan-Hsing Wu ,  Tung-Yuan Chen ,  Chao-Yi Wu

发明人： Lien-Hsun Ho ,  Yuan-Liang Hsu ,  Shou-Ting Yeh ,  Chuan-Hsing Wu ,  Tung-Yuan Chen ,  Chao-Yi Wu

IPC分类号： H01R13/627

CPC分类号： H01R13/6272 ,  H01R13/5833 ,  H01R13/6335

摘要： An auxiliary device for a connector has a body, a wire unit and plug. The wire unit is mounted securely in the body and extends out of the body from a first end of the body. The plug is formed on a second end of the body and is perpendicular to the wire unit. Therefore, the position of the wire unit is fixed when the plug is inserted into a socket.

公开(公告)号：US08769188B2

公开(公告)日：2014-07-01

申请号：US12620722

申请日：2009-11-18

申请人： Li-Chun Tu ,  Chao-Yi Wu ,  Ping-Sheng Chen

发明人： Li-Chun Tu ,  Chao-Yi Wu ,  Ping-Sheng Chen

IPC分类号： G06F11/00 ,  H03M13/09 ,  G06F3/06

CPC分类号： H03M13/09 ,  G06F3/0608 ,  G06F3/0616 ,  G06F3/0641 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7209 ,  H03M13/096

摘要： The invention provides a nonvolatile memory controller. In one embodiment, the nonvolatile memory controller receives new data for writing a nonvolatile memory from a host, and comprises a signature calculating circuit, a signature buffer, a signature comparison circuit, a data comparison circuit, and a nonvolatile memory interface circuit. The signature calculating circuit calculates a first signature according to the new data. The signature buffer outputs a second signature corresponding to old data stored in the nonvolatile memory, wherein the old data has the same logical address as that of the new data. The signature comparison circuit determines whether the first signature is identical to the second signature. The nonvolatile memory interface circuit writes the new data to the nonvolatile memory when the first signature is determined to be different from the second signature by the signature comparison circuit.

摘要翻译： 本发明提供一种非易失性存储器控制器。 在一个实施例中，非易失性存储器控制器接收用于从主机写入非易失性存储器的新数据，并且包括签名计算电路，签名缓冲器，签名比较电路，数据比较电路和非易失性存储器接口电路。 签名计算电路根据新数据计算第一签名。 签名缓冲器输出对应于存储在非易失性存储器中的旧数据的第二签名，其中旧数据具有与新数据相同的逻辑地址。 签名比较电路确定第一签名是否与第二签名相同。 当通过签名比较电路确定第一签名与第二签名不同时，非易失性存储器接口电路将新数据写入非易失性存储器。