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    Memory system and memory device having a serial interface
    1.
    发明授权
    Memory system and memory device having a serial interface 有权
    具有串行接口的存储器系统和存储器件

    公开(公告)号：US07167410B2

    公开(公告)日：2007-01-23

    申请号：US11114807

    申请日：2005-04-26

    申请人： Charles Boecker ,  Scott Irwin ,  Matthew Shafer ,  Eric Groen ,  Aaron Hoelscher ,  Andrew Jenkins ,  David Black

    发明人： Charles Boecker ,  Scott Irwin ,  Matthew Shafer ,  Eric Groen ,  Aaron Hoelscher ,  Andrew Jenkins ,  David Black

    IPC分类号： G11C8/00

    CPC分类号： G11C8/04 ,  G11C7/1006 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/107

    摘要： A memory device and system are disclosed that may include a serial data interface, a serial address interface, and a reference clock interface. The reference clock interface is configured to receive a signal from a reference clock source that provides a reference clock signal to a memory control device. The serial interfaces are coupled to other memory devices or memory control devices. A method of transferring data within a memory system using serial interfaces is also disclosed. The method includes performing clock multiplication on a reference clock to provide a multiplied clock, using the multiplied clock to serialize and transmit data onto a serial interface, recovering data from the seal interface, using the reference clock to determine an initial frequency for use by clock and data recovery module, using the data recovered from the serial interface to determine a phase and final frequency of a recovered clock, and using the recovered clock to de-serialize received serial data into parallel data words.

    摘要翻译： 公开了一种可以包括串行数据接口，串行地址接口和参考时钟接口的存储器件和系统。 参考时钟接口被配置为从参考时钟源接收信号，该信号将参考时钟信号提供给存储器控制装置。 串行接口耦合到其他存储器设备或存储器控制设备。 还公开了使用串行接口在存储器系统内传送数据的方法。 该方法包括在参考时钟上执行时钟倍增以提供倍增时钟，使用倍增时钟将数据串行化并传输到串行接口，从密封接口恢复数据，使用参考时钟确定时钟使用的初始频率 和数据恢复模块，使用从串行接口恢复的数据来确定恢复的时钟的相位和最终频率，并且使用恢复的时钟将接收到的串行数据解码为并行数据字。

    Memory system and memory device having a serial interface
    2.
    发明申请
    Memory system and memory device having a serial interface 有权
    具有串行接口的存储器系统和存储器件

    公开(公告)号：US20060239107A1

    公开(公告)日：2006-10-26

    申请号：US11114807

    申请日：2005-04-26

    申请人： Charles Boecker ,  Scott Irwin ,  Matthew Shafer ,  Eric Groen ,  Aaron Hoelscher ,  Andrew Jenkins ,  David Black

    发明人： Charles Boecker ,  Scott Irwin ,  Matthew Shafer ,  Eric Groen ,  Aaron Hoelscher ,  Andrew Jenkins ,  David Black

    IPC分类号： G11C8/00

    CPC分类号： G11C8/04 ,  G11C7/1006 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/107

    摘要： A memory device and system are disclosed that may include a serial data interface, a serial address interface, and a reference clock interface. The reference clock interface is configured to receive a signal from a reference clock source that provides a reference clock signal to a memory control device. The serial interfaces are coupled to other memory devices or memory control devices. A method of transferring data within a memory system using serial interfaces is also disclosed. The method includes performing clock multiplication on a reference clock to provide a multiplied clock, using the multiplied clock to serialize and transmit data onto a serial interface, recovering data from the seal interface, using the reference clock to determine an initial frequency for use by clock and data recovery module, using the data recovered from the serial interface to determine a phase and final frequency of a recovered clock, and using the recovered clock to de-serialize received serial data into parallel data words.

    摘要翻译： 公开了一种可以包括串行数据接口，串行地址接口和参考时钟接口的存储器件和系统。 参考时钟接口被配置为从参考时钟源接收信号，该信号将参考时钟信号提供给存储器控制装置。 串行接口耦合到其他存储器设备或存储器控制设备。 还公开了使用串行接口在存储器系统内传送数据的方法。 该方法包括在参考时钟上执行时钟倍增以提供倍增时钟，使用倍增时钟将数据串行化并传输到串行接口，从密封接口恢复数据，使用参考时钟确定时钟使用的初始频率 和数据恢复模块，使用从串行接口恢复的数据来确定恢复的时钟的相位和最终频率，并且使用恢复的时钟将接收到的串行数据解码为并行数据字。

    METHOD AND APPARATUS TO ENCODE AND SYNCHRONIZE A SERIAL INTERFACE
    3.
    发明申请
    METHOD AND APPARATUS TO ENCODE AND SYNCHRONIZE A SERIAL INTERFACE 有权
    编码和同步串行接口的方法和装置

    公开(公告)号：US20090316728A1

    公开(公告)日：2009-12-24

    申请号：US12548135

    申请日：2009-08-26

    申请人： Charles Boecker ,  Scott Irwin ,  Matthew Shafer ,  Eric Groen ,  Aaron Hoelscher ,  Andrew Jenkins ,  David Black

    发明人： Charles Boecker ,  Scott Irwin ,  Matthew Shafer ,  Eric Groen ,  Aaron Hoelscher ,  Andrew Jenkins ,  David Black

    IPC分类号： H04J3/06

    CPC分类号： H04L7/10 ,  G11C7/1006 ,  H04L25/03866 ,  H04L25/4904 ,  H04L25/491

    摘要： The present disclosure is generally directed to a method and apparatus to communicate data between two or more semiconductor devices. In an embodiment, a method includes synchronizing a master device with a slave device, where the master device includes a semiconductor device. Synchronizing includes transmitting a first synchronization marker data pattern via a first serial interface from the master device at a first time, and receiving a second synchronization marker data pattern via a second serial interface at the master device at a second time in response to transmitting the first synchronization marker data pattern. Synchronizing also includes determining, based at least in part on the first time and the second time, a third time when a reply is to be received by the master device in response to a request transmitted from the master device to the slave device.

    摘要翻译： 本公开一般涉及在两个或更多个半导体器件之间传送数据的方法和装置。 在一个实施例中，一种方法包括使主设备与从设备同步，其中主设备包括半导体设备。 同步包括在第一时间通过第一串行接口从主设备发送第一同步标记数据模式，以及响应于发送第一同步标记数据模式，通过主设备上的第二串行接口在第二时间接收第二同步标记数据模式 同步标记数据模式。 同步还包括至少部分地基于第一时间和第二时间响应于从主设备向从设备发送的请求而主要设备接收到应答的第三次。

    Method and apparatus to encode and synchronize a serial interface
    5.
    发明授权
    Method and apparatus to encode and synchronize a serial interface 有权
    串行接口编码和同步的方法和装置

    公开(公告)号：US08135037B2

    公开(公告)日：2012-03-13

    申请号：US12548135

    申请日：2009-08-26

    申请人： Charles Boecker ,  Scott Irwin ,  Matthew Shafer ,  Eric Groen ,  Aaron Hoelscher ,  Andrew Jenkins ,  David Black

    发明人： Charles Boecker ,  Scott Irwin ,  Matthew Shafer ,  Eric Groen ,  Aaron Hoelscher ,  Andrew Jenkins ,  David Black

    IPC分类号： H04J3/06 ,  H03M13/03

    CPC分类号： H04L7/10 ,  G11C7/1006 ,  H04L25/03866 ,  H04L25/4904 ,  H04L25/491

    摘要： The present disclosure is generally directed to a method and apparatus to communicate data between two or more semiconductor devices. In an embodiment, a method includes synchronizing a master device with a slave device, where the master device includes a semiconductor device. Synchronizing includes transmitting a first synchronization marker data pattern via a first serial interface from the master device at a first time, and receiving a second synchronization marker data pattern via a second serial interface at the master device at a second time in response to transmitting the first synchronization marker data pattern. Synchronizing also includes determining, based at least in part on the first time and the second time, a third time when a reply is to be received by the master device in response to a request transmitted from the master device to the slave device.

    摘要翻译： 本公开一般涉及在两个或更多个半导体器件之间传送数据的方法和装置。 在一个实施例中，一种方法包括使主设备与从设备同步，其中主设备包括半导体设备。 同步包括在第一时间通过第一串行接口从主设备发送第一同步标记数据模式，以及响应于发送第一同步标记数据模式，通过主设备上的第二串行接口在第二时间接收第二同步标记数据模式 同步标记数据模式。 同步还包括至少部分地基于第一时间和第二时间响应于从主设备向从设备发送的请求而主要设备接收到应答的第三次。

    Programmable logic device including programmable multi-gigabit transceivers
    7.
    发明申请
    Programmable logic device including programmable multi-gigabit transceivers 有权
    可编程逻辑器件包括可编程的多吉比特收发器

    公开(公告)号：US20050058187A1

    公开(公告)日：2005-03-17

    申请号：US10661016

    申请日：2003-09-11

    申请人： Eric Groen ,  Charles Boecker ,  William Black ,  Scott Irwin ,  Joseph Kryzak ,  Yiqin Chen ,  Andrew Jenkins ,  Aaron Hoelscher

    发明人： Eric Groen ,  Charles Boecker ,  William Black ,  Scott Irwin ,  Joseph Kryzak ,  Yiqin Chen ,  Andrew Jenkins ,  Aaron Hoelscher

    IPC分类号： G06F15/78 ,  H04L25/14 ,  H04B1/38

    CPC分类号： H04L25/14

    摘要： A programmable logic device includes a plurality of programmable multi-gigabit transceivers, programmable logic fabric, and a control module. Each of the plurality of programmable multi-gigabit transceivers is individually programmed to a desired transceiving mode of operation in accordance with a plurality of transceiver settings. The programmable logic fabric is operably coupled to the plurality of programmable multi-gigabit transceivers and is configured to process at least a portion of the data being transceived via the multi-gigabit transceivers. The control module is operably coupled to produce the plurality of transceiver settings based on a desired mode of operation for the programmable logic device.

    摘要翻译： 可编程逻辑器件包括多个可编程的多吉比特收发器，可编程逻辑结构和控制模块。 根据多个收发器设置，多个可编程的多吉比特收发器中的每一个被单独编程为期望的收发操作模式。 可编程逻辑结构可操作地耦合到多个可编程的多吉比特收发器，并且被配置为处理经由多吉比特收发器收发的数据的至少一部分。 控制模块可操作地耦合以基于可编程逻辑器件的期望操作模式产生多个收发器设置。

    Framing of transmit encoded data and linear feedback shifting
    8.
    发明申请
    Framing of transmit encoded data and linear feedback shifting 有权
    发送编码数据的帧和线性反馈移位

    公开(公告)号：US20050058290A1

    公开(公告)日：2005-03-17

    申请号：US10659979

    申请日：2003-09-11

    申请人： Joseph Kryzak ,  Aaron Hoelscher

    发明人： Joseph Kryzak ,  Aaron Hoelscher

    IPC分类号： H04L25/03 ,  H04L9/00

    CPC分类号： H04L25/03866

    摘要： Framing transmit encoded output data begins by determining a scrambling remainder between scrambling of an input code word in accordance with a 1st scrambling protocol and the scrambling of the input code word in accordance with an adjustable scrambling protocol. The processing continues by adjusting the adjustable scrambling protocol based on the scrambling remainder to produce an adjusted scrambling protocol. The processing continues by scrambling the input code word in accordance with the 1st scrambling protocol to produce a 1st scrambled code word. The processing continues by scrambling the input code word in accordance with the adjusted scrambling protocol to produce a scrambled partial code word. The processing continues by determining a portion of the 1st scrambled code word based on the scrambling remainder. The process continues by combining the scrambled partial code word with the portion of the 1st scrambled code word to produce the transmit encoded output data.

    摘要翻译： 成帧发送编码的输出数据通过根据可调扰的加扰协议确定根据第1加扰协议的输入码字的加扰和输入码字的加扰之间的加扰余数开始。 该处理继续通过基于加扰余数来调整可调扰码协议以产生经调整的加扰协议。 通过根据第1个加扰协议对输入的代码字进行加扰以产生第1个加扰码字，继续进行处理。 该处理通过根据调整后的加扰协议对输入的代码字进行加扰以产生加扰的部分代码字而继续进行。 该处理通过基于加扰余数来确定第一个加扰码字的一部分来继续。 该过程通过将加扰的部分码字与第1个加扰码字的部分组合以产生发送编码的输出数据而继续。

    Channel bonding of a plurality of multi-gigabit transceivers
    9.
    发明申请
    Channel bonding of a plurality of multi-gigabit transceivers 有权
    多个千兆位收发器的信道绑定

    公开(公告)号：US20050058186A1

    公开(公告)日：2005-03-17

    申请号：US10659974

    申请日：2003-09-11

    申请人： Joseph Kryzak ,  Aaron Hoelscher ,  Thomas Rock

    发明人： Joseph Kryzak ,  Aaron Hoelscher ,  Thomas Rock

    IPC分类号： H04L25/14 ,  H04B1/38

    CPC分类号： H04L25/14

    摘要： A method for channel bonding begins when a master transceiver receives a channel bonding sequence. The process continues with the master transceiver generating a channel bonding request and transmitting it and channel bonding configuration information to the slave transceiver. The process continues with each slave receiving the channel bonding sequence, the channel bonding request and the channel bonding configuration information. The process continues as each slave processes the channel bonding request and the channel bonding sequence in accordance with the channel bonding configuration information to determine individual slave channel bonding start information. The process continues as the master processes the channel bonding sequence in accordance with the channel bonding configuration information and the channel bonding request to determine master channel bonding start information.

    摘要翻译： 当主收发器接收到信道绑定序列时，开始通道绑定的方法。 该过程继续，主收发器产生信道绑定请求并将其发送，并将绑定配置信息传送到从收发器。 该过程继续，每个从机接收信道绑定序列，信道绑定请求和信道绑定配置信息。 该过程继续，因为每个从机根据信道绑定配置信息处理信道绑定请求和信道绑定序列，以确定单独的从属信道绑定开始信息。 当主设备根据信道绑定配置信息和信道绑定请求处理信道绑定序列以确定主信道绑定开始信息时，该过程继续。