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    Memory system and memory device having a serial interface
    1.
    发明授权
    Memory system and memory device having a serial interface 有权
    具有串行接口的存储器系统和存储器件

    公开(公告)号：US07167410B2

    公开(公告)日：2007-01-23

    申请号：US11114807

    申请日：2005-04-26

    申请人： Charles Boecker ,  Scott Irwin ,  Matthew Shafer ,  Eric Groen ,  Aaron Hoelscher ,  Andrew Jenkins ,  David Black

    发明人： Charles Boecker ,  Scott Irwin ,  Matthew Shafer ,  Eric Groen ,  Aaron Hoelscher ,  Andrew Jenkins ,  David Black

    IPC分类号： G11C8/00

    CPC分类号： G11C8/04 ,  G11C7/1006 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/107

    摘要： A memory device and system are disclosed that may include a serial data interface, a serial address interface, and a reference clock interface. The reference clock interface is configured to receive a signal from a reference clock source that provides a reference clock signal to a memory control device. The serial interfaces are coupled to other memory devices or memory control devices. A method of transferring data within a memory system using serial interfaces is also disclosed. The method includes performing clock multiplication on a reference clock to provide a multiplied clock, using the multiplied clock to serialize and transmit data onto a serial interface, recovering data from the seal interface, using the reference clock to determine an initial frequency for use by clock and data recovery module, using the data recovered from the serial interface to determine a phase and final frequency of a recovered clock, and using the recovered clock to de-serialize received serial data into parallel data words.

    摘要翻译： 公开了一种可以包括串行数据接口，串行地址接口和参考时钟接口的存储器件和系统。 参考时钟接口被配置为从参考时钟源接收信号，该信号将参考时钟信号提供给存储器控制装置。 串行接口耦合到其他存储器设备或存储器控制设备。 还公开了使用串行接口在存储器系统内传送数据的方法。 该方法包括在参考时钟上执行时钟倍增以提供倍增时钟，使用倍增时钟将数据串行化并传输到串行接口，从密封接口恢复数据，使用参考时钟确定时钟使用的初始频率 和数据恢复模块，使用从串行接口恢复的数据来确定恢复的时钟的相位和最终频率，并且使用恢复的时钟将接收到的串行数据解码为并行数据字。

    Memory system and memory device having a serial interface
    2.
    发明申请
    Memory system and memory device having a serial interface 有权
    具有串行接口的存储器系统和存储器件

    公开(公告)号：US20060239107A1

    公开(公告)日：2006-10-26

    申请号：US11114807

    申请日：2005-04-26

    申请人： Charles Boecker ,  Scott Irwin ,  Matthew Shafer ,  Eric Groen ,  Aaron Hoelscher ,  Andrew Jenkins ,  David Black

    发明人： Charles Boecker ,  Scott Irwin ,  Matthew Shafer ,  Eric Groen ,  Aaron Hoelscher ,  Andrew Jenkins ,  David Black

    IPC分类号： G11C8/00

    CPC分类号： G11C8/04 ,  G11C7/1006 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/107

    摘要： A memory device and system are disclosed that may include a serial data interface, a serial address interface, and a reference clock interface. The reference clock interface is configured to receive a signal from a reference clock source that provides a reference clock signal to a memory control device. The serial interfaces are coupled to other memory devices or memory control devices. A method of transferring data within a memory system using serial interfaces is also disclosed. The method includes performing clock multiplication on a reference clock to provide a multiplied clock, using the multiplied clock to serialize and transmit data onto a serial interface, recovering data from the seal interface, using the reference clock to determine an initial frequency for use by clock and data recovery module, using the data recovered from the serial interface to determine a phase and final frequency of a recovered clock, and using the recovered clock to de-serialize received serial data into parallel data words.

    摘要翻译： 公开了一种可以包括串行数据接口，串行地址接口和参考时钟接口的存储器件和系统。 参考时钟接口被配置为从参考时钟源接收信号，该信号将参考时钟信号提供给存储器控制装置。 串行接口耦合到其他存储器设备或存储器控制设备。 还公开了使用串行接口在存储器系统内传送数据的方法。 该方法包括在参考时钟上执行时钟倍增以提供倍增时钟，使用倍增时钟将数据串行化并传输到串行接口，从密封接口恢复数据，使用参考时钟确定时钟使用的初始频率 和数据恢复模块，使用从串行接口恢复的数据来确定恢复的时钟的相位和最终频率，并且使用恢复的时钟将接收到的串行数据解码为并行数据字。

    Method and apparatus to encode and synchronize a serial interface
    3.
    发明授权
    Method and apparatus to encode and synchronize a serial interface 有权
    串行接口编码和同步的方法和装置

    公开(公告)号：US08135037B2

    公开(公告)日：2012-03-13

    申请号：US12548135

    申请日：2009-08-26

    申请人： Charles Boecker ,  Scott Irwin ,  Matthew Shafer ,  Eric Groen ,  Aaron Hoelscher ,  Andrew Jenkins ,  David Black

    发明人： Charles Boecker ,  Scott Irwin ,  Matthew Shafer ,  Eric Groen ,  Aaron Hoelscher ,  Andrew Jenkins ,  David Black

    IPC分类号： H04J3/06 ,  H03M13/03

    CPC分类号： H04L7/10 ,  G11C7/1006 ,  H04L25/03866 ,  H04L25/4904 ,  H04L25/491

    摘要： The present disclosure is generally directed to a method and apparatus to communicate data between two or more semiconductor devices. In an embodiment, a method includes synchronizing a master device with a slave device, where the master device includes a semiconductor device. Synchronizing includes transmitting a first synchronization marker data pattern via a first serial interface from the master device at a first time, and receiving a second synchronization marker data pattern via a second serial interface at the master device at a second time in response to transmitting the first synchronization marker data pattern. Synchronizing also includes determining, based at least in part on the first time and the second time, a third time when a reply is to be received by the master device in response to a request transmitted from the master device to the slave device.

    摘要翻译： 本公开一般涉及在两个或更多个半导体器件之间传送数据的方法和装置。 在一个实施例中，一种方法包括使主设备与从设备同步，其中主设备包括半导体设备。 同步包括在第一时间通过第一串行接口从主设备发送第一同步标记数据模式，以及响应于发送第一同步标记数据模式，通过主设备上的第二串行接口在第二时间接收第二同步标记数据模式 同步标记数据模式。 同步还包括至少部分地基于第一时间和第二时间响应于从主设备向从设备发送的请求而主要设备接收到应答的第三次。

    METHOD AND APPARATUS TO ENCODE AND SYNCHRONIZE A SERIAL INTERFACE
    5.
    发明申请
    METHOD AND APPARATUS TO ENCODE AND SYNCHRONIZE A SERIAL INTERFACE 有权
    编码和同步串行接口的方法和装置

    公开(公告)号：US20090316728A1

    公开(公告)日：2009-12-24

    申请号：US12548135

    申请日：2009-08-26

    申请人： Charles Boecker ,  Scott Irwin ,  Matthew Shafer ,  Eric Groen ,  Aaron Hoelscher ,  Andrew Jenkins ,  David Black

    发明人： Charles Boecker ,  Scott Irwin ,  Matthew Shafer ,  Eric Groen ,  Aaron Hoelscher ,  Andrew Jenkins ,  David Black

    IPC分类号： H04J3/06

    CPC分类号： H04L7/10 ,  G11C7/1006 ,  H04L25/03866 ,  H04L25/4904 ,  H04L25/491

    摘要： The present disclosure is generally directed to a method and apparatus to communicate data between two or more semiconductor devices. In an embodiment, a method includes synchronizing a master device with a slave device, where the master device includes a semiconductor device. Synchronizing includes transmitting a first synchronization marker data pattern via a first serial interface from the master device at a first time, and receiving a second synchronization marker data pattern via a second serial interface at the master device at a second time in response to transmitting the first synchronization marker data pattern. Synchronizing also includes determining, based at least in part on the first time and the second time, a third time when a reply is to be received by the master device in response to a request transmitted from the master device to the slave device.

    摘要翻译： 本公开一般涉及在两个或更多个半导体器件之间传送数据的方法和装置。 在一个实施例中，一种方法包括使主设备与从设备同步，其中主设备包括半导体设备。 同步包括在第一时间通过第一串行接口从主设备发送第一同步标记数据模式，以及响应于发送第一同步标记数据模式，通过主设备上的第二串行接口在第二时间接收第二同步标记数据模式 同步标记数据模式。 同步还包括至少部分地基于第一时间和第二时间响应于从主设备向从设备发送的请求而主要设备接收到应答的第三次。

    Programmable logic device including programmable multi-gigabit transceivers
    7.
    发明申请
    Programmable logic device including programmable multi-gigabit transceivers 有权
    可编程逻辑器件包括可编程的多吉比特收发器

    公开(公告)号：US20050058187A1

    公开(公告)日：2005-03-17

    申请号：US10661016

    申请日：2003-09-11

    申请人： Eric Groen ,  Charles Boecker ,  William Black ,  Scott Irwin ,  Joseph Kryzak ,  Yiqin Chen ,  Andrew Jenkins ,  Aaron Hoelscher

    发明人： Eric Groen ,  Charles Boecker ,  William Black ,  Scott Irwin ,  Joseph Kryzak ,  Yiqin Chen ,  Andrew Jenkins ,  Aaron Hoelscher

    IPC分类号： G06F15/78 ,  H04L25/14 ,  H04B1/38

    CPC分类号： H04L25/14

    摘要： A programmable logic device includes a plurality of programmable multi-gigabit transceivers, programmable logic fabric, and a control module. Each of the plurality of programmable multi-gigabit transceivers is individually programmed to a desired transceiving mode of operation in accordance with a plurality of transceiver settings. The programmable logic fabric is operably coupled to the plurality of programmable multi-gigabit transceivers and is configured to process at least a portion of the data being transceived via the multi-gigabit transceivers. The control module is operably coupled to produce the plurality of transceiver settings based on a desired mode of operation for the programmable logic device.

    摘要翻译： 可编程逻辑器件包括多个可编程的多吉比特收发器，可编程逻辑结构和控制模块。 根据多个收发器设置，多个可编程的多吉比特收发器中的每一个被单独编程为期望的收发操作模式。 可编程逻辑结构可操作地耦合到多个可编程的多吉比特收发器，并且被配置为处理经由多吉比特收发器收发的数据的至少一部分。 控制模块可操作地耦合以基于可编程逻辑器件的期望操作模式产生多个收发器设置。

    System and method for web service billing
    8.
    发明申请
    System and method for web service billing 审中-公开
    用于Web服务计费的系统和方法

    公开(公告)号：US20050065879A1

    公开(公告)日：2005-03-24

    申请号：US10666631

    申请日：2003-09-18

    申请人： Robert Birch ,  Scott Irwin ,  Joseph Lupo ,  Steve Weagraff

    发明人： Robert Birch ,  Scott Irwin ,  Joseph Lupo ,  Steve Weagraff

    IPC分类号： G06Q30/00 ,  G06F17/60

    CPC分类号： G06Q30/04 ,  G06Q20/102

    摘要： A method and system is disclosed herein for decoupling billing for web services from the application logic which governs those web services by instrumenting a web services stack to monitor SOAP envelopes for pre-determined elements and to use those elements to determine questions as to authorization for solvency as well as calculate charges for said web services.

    摘要翻译： 本文公开了一种方法和系统，用于将网络服务的计费从用于管理这些web服务的应用程序逻辑中去除，该方法和系统通过调整web服务堆栈来监视预定元素的SOAP包络并使用这些元素来确定关于偿付能力授权的问题 以及计算所述网络服务的费用。

    Method and system for hierarchy based contact routing
    9.
    发明授权
    Method and system for hierarchy based contact routing 有权
    基于层次结构的联系路由的方法和系统

    公开(公告)号：US08588398B1

    公开(公告)日：2013-11-19

    申请号：US13208052

    申请日：2011-08-11

    申请人： Scott Irwin ,  Kishore Korimilli

    发明人： Scott Irwin ,  Kishore Korimilli

    IPC分类号： H04M3/00

    CPC分类号： H04M3/5238

    摘要： Resource allocation in a contact center can be performed using a network of nodes. Such a network of nodes can be organized according into resource nodes, domain nodes, and service nodes, with paths from the domain nodes, through the service nodes, to the resource nodes being used in the allocation.

    摘要翻译： 可以使用节点网络来执行联络中心中的资源分配。 这样的节点网络可以根据资源节点，域节点和服务节点，从域节点，服务节点到分配中使用的资源节点的路径进行组织。

    PMA RX in course loop for high speed sampling
    10.
    发明申请
    PMA RX in course loop for high speed sampling 有权
    PMA RX在高速采样过程中循环

    公开(公告)号：US20070201541A1

    公开(公告)日：2007-08-30

    申请号：US11796111

    申请日：2007-04-25

    申请人： Jerry Chuang ,  William Black ,  Scott Irwin

    发明人： Jerry Chuang ,  William Black ,  Scott Irwin

    IPC分类号： H04B1/38

    CPC分类号： H03L7/18 ,  H03L7/087 ,  H03L7/113 ,  H03L7/14 ,  H04L7/033

    摘要： A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.

    摘要翻译： 用于处理高数据速率串行数据的设备和方法包括用于基于高数据速率输入数据流来恢复时钟的电路。 收发器包括选择性地提供具有在指定量内的精度的时钟的锁相环的粗略回路。 在采样操作模式中，只有粗环路PLL被耦合以提供可以从其导出振荡信号和时钟的误差信号。 在第二模式（锁定）操作中，收发器可以通过耦合精细环路PLL来提供经调整的误差信号来锁定到接收到的串行数据流。 在第三种操作模式中，（自动）收发器最初通过去耦合精细环路PLL并耦合粗环路PLL直到达到稳定状态来执行粗略校准。