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1.发明授权公开(公告)号：US07296252B2
公开(公告)日：2007-11-13
申请号：US10996293
申请日：2004-11-22
CPC分类号： G06F17/5072 , G06F17/50
摘要： A placement technique for designing a layout of an integrated circuit by calculating clustering scores for different pairs of objects in the layout based on connections of two objects in a given pair and the sizes of the two objects, then grouping at least one of the pairs of objects into a cluster based on the clustering scores, partitioning the objects as clustered and ungrouping the cluster after partitioning. The pair of objects having the highest clustering score are grouped into the cluster, and the clustering score is directly proportional to the total weight of connections between the two objects in the respective pair. The clustering scores are preferably inserted in a binary heap to identify the highest clustering score. After grouping, the clustering score for any neighboring object of a clustered object is marked to indicate that the clustering score is invalid and must be recalculated. The calculating and grouping are then repeated iteratively based on the previous clustered layout. Cluster growth can be controlled indirectly, or controlled directly by imposing an upper bound on cluster size.
摘要翻译： 一种用于通过基于给定对中的两个对象的连接和两个对象的大小的布局来计算布局中的不同对对象的聚类分数来设计集成电路的布局的布局技术，然后将至少一个对 对象基于聚类分数进入群集，将对象分区为群集，并在分区后取消分组群集。 具有最高聚类分数的一对对象被分组到聚类中，并且聚类分数与相应对中的两个对象之间的连接的总权重成正比。 聚类分数优选插入二进制堆中以识别最高聚类分数。 分组后，将聚类对象的任何邻近对象的聚类分数标记为表示聚类分数无效并且必须重新计算。 然后基于先前的聚类布局迭代地重复计算和分组。 群集增长可以间接控制，也可以通过对群集大小施加上限直接控制。
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2.发明授权Stability metrics for placement to quantify the stability of placement algorithms 有权放置的稳定性指标来量化放置算法的稳定性公开(公告)号：US07073144B2
公开(公告)日：2006-07-04
申请号：US10825148
申请日：2004-04-15
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of assessing the stability of a placement tool used in designing the physical layout of an integrated circuit chip, by constructing different layouts of cells using the placement tool with different sets of input parameters, and calculating a stability value based on the movement of respective cell locations between the layouts. The stability value can be normalized based on cell locations in a random placement. One stability metric measures absolute movement of individual cells in the layouts, weighted by cell area. The cell movements can be squared in calculating the stability value. Another stability metric measures the relative movement of cells with respect to their nets. Shifting of cells and symmetric reversal of cells about a net center does not contribute to this relative movement, but spreading of cells and rotation of cells with respect to the net center does contribute to the relative movement. Relative cell movements can again be squared in calculating the stability value. Many different layouts can be designed using the same placement tool with a range of different input parameters and different movement metrics to build a collection of comparative values that can be used to identify stability characteristics for that tool.
摘要翻译： 一种评估用于设计集成电路芯片的物理布局的放置工具的稳定性的方法，通过使用具有不同输入参数集合的放置工具构造不同的单元布局，以及基于相应的运动来计算稳定性值 单元格位置之间的布局。 稳定性值可以根据随机位置中的单元格位置进行归一化。 一个稳定度度量衡量单元格在布局中的绝对运动，由单元格区域加权。 在计算稳定性值时，单元格移动可以平方。 另一个稳定度量度衡量细胞相对于网的相对运动。 细胞的移位和细胞对网络中心的对称反转对这种相对运动没有贡献，但是细胞的扩散和细胞的相对于网络中心的旋转确实有助于相对运动。 在计算稳定性值时，相对单元移动可以再次平方。 可以使用具有一系列不同输入参数和不同运动度量的相同放置工具来设计许多不同的布局，以构建可用于识别该工具的稳定性特征的比较值集合。
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公开(公告)号：US07020861B2
公开(公告)日：2006-03-28
申请号：US10621950
申请日：2003-07-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5072
摘要： A method of designing an integrated circuit including executing a placement algorithm to place a set of objects within the integrated circuit. The set of objects includes latched objects and non-latched objects. The algorithm places objects to minimize clock signal delay subject to a constraint on the placement distribution of the latched objects relative to the placement distribution of the non-latched objects. The latched object and non-latched object placement constraints may limit the difference between the latched object center of mass and a non-latched object center of mass. The latched object center of mass equals a sum of size-location products for each latched object divided by the sum of sizes for each latched object. The constraints may require that the latched object center of mass and the non-latched center of mass both equal the center of mass for all objects.
摘要翻译： 一种设计集成电路的方法，包括执行放置算法以将一组对象放置在集成电路内。 对象集包括锁存对象和非锁定对象。 该算法使对象最小化时钟信号延迟，受限于锁存对象相对于非锁定对象的位置分布的位置分布。 锁定对象和非锁定对象放置约束可能会限制被锁定的物体质心和未锁定的物体质心之间的差异。 被锁定的物体质心等于每个被锁定物体的大小位置乘积之和除以每个锁定物体的大小之和。 约束可能要求被锁定的物体质心和非锁定质心均等于所有物体的质心。
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公开(公告)号：US06996512B2
公开(公告)日：2006-02-07
申请号：US09838429
申请日：2001-04-19
CPC分类号： G06F17/5072
摘要： A method, system, and computer program product for allocating buffer and wire placement in an integrated circuit design is provided. In one embodiment, the surface of a integrated circuit design is represented as a tile graph. Allocation of buffer locations for selected tiles in the tile graph is then received and nets are routed between associated sources and sinks. Buffer locations within selected tiles are then selectively assigned based upon buffer needs of the nets, wherein the nets are routed through selected tiles and assigned buffer locations using a cost minimization algorithm.
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5.发明申请SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DIFFUSION BASED CELL PLACEMENT MIGRATION 有权用于基于扩散的电池放置移动的系统和计算机程序产品公开(公告)号：US20090064074A1
公开(公告)日：2009-03-05
申请号：US12264619
申请日：2008-11-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system and computer program product for cell placement in an integrated circuit design that uses a calculated diffusion velocity determined from a density value in order to relocate the cells until the cell placement reduces the density below a predetermined threshold. The method acts to control the movement of different cells to reduce the density of the cells prior to legalization of the cell placement.
摘要翻译： 一种用于在集成电路设计中用于单元放置的系统和计算机程序产品，其使用从密度值确定的计算的扩散速度，以便重新定位单元直到单元布置将密度降低到低于预定阈值。 该方法用于控制不同细胞的运动，以在细胞放置合法化之前降低细胞的密度。
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公开(公告)号：US07464356B2
公开(公告)日：2008-12-09
申请号：US11304955
申请日：2005-12-15
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method for cell placement in an integrated circuit design that uses a calculated diffusion velocity determined from a density value in order to relocate the cells until the cell placement reduces the density below a predetermined threshold. The method acts to control the movement of different cells to reduce the density of the cells prior to legalization of the cell placement.
摘要翻译： 一种集成电路设计中的细胞放置方法，其使用从密度值确定的计算的扩散速度，以便重新定位细胞，直到细胞放置将密度降低到低于预定阈值。 该方法用于控制不同细胞的运动，以在细胞放置合法化之前降低细胞的密度。
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7.发明授权Method and apparatus for applying fine-grained transforms during placement synthesis interaction 失效在放置合成相互作用期间应用细粒度变换的方法和装置公开(公告)号：US07047163B1
公开(公告)日：2006-05-16
申请号：US09524408
申请日：2000-03-13
申请人： Kanad Chakraborty , Wilm Ernst Donath , Prabhakar Nandavar Kudva , Lakshmi Narasimha Reddy , Leon Stok , Andrew James Sullivan , Paul Gerard Villarrubia
发明人： Kanad Chakraborty , Wilm Ernst Donath , Prabhakar Nandavar Kudva , Lakshmi Narasimha Reddy , Leon Stok , Andrew James Sullivan , Paul Gerard Villarrubia
CPC分类号： G06F17/5045 , G06F17/5072
摘要： A method (and system) of applying transforms for modifying a plurality of domains concurrently in a design space, includes creating a sequence of more and less granular placement and netlist modification transforms. A converging design process flow is created by a flexible mechanism in which a select combination of fine-grained transforms are applied to optimize the netlist and placement of a design.
摘要翻译： 在设计空间中同时应用用于修改多个域的变换的方法（和系统）包括创建越来越少的粒度位置和网表修改变换的序列。 融合设计流程由灵活的机制创建，其中应用细粒度变换的选择组合来优化设计的网表和布局。
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8.发明授权Windowing mechanism for reducing pessimism in cross-talk analysis of digital chips 失效数字芯片串扰分析中减少悲观的窗口化机制公开(公告)号：US06510540B1
公开(公告)日：2003-01-21
申请号：US09640540
申请日：2000-08-17
申请人： Byron Lee Krauter , Sharad Mehrotra , Jonathan Humphrey Saxman , Paul Gerard Villarrubia , David J. Widiger
发明人： Byron Lee Krauter , Sharad Mehrotra , Jonathan Humphrey Saxman , Paul Gerard Villarrubia , David J. Widiger
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： This invention reduces pessimism in cross talk analysis of digital circuits by combining only the peak noises from aggressor nets that can switch simultaneously during the time interval when the downstream receiving latch can sample the errant data. This is done by, first, determining aggressor switching windows and victim sensitivity windows. These windows are then used to determine which combination of noise sources can temporally align so as to cause the greatest noise within the victim sensitivity window.
摘要翻译： 本发明通过仅在来自下游接收锁存器可以对错误数据进行采样的时间间隔期间同时切换的来自侵略者网络的峰值噪声组合来减少数字电路的串扰分析中的悲观情绪。 这是通过首先确定侵略者切换窗口和受害者敏感性窗口来完成的。 然后，这些窗口用于确定噪声源的哪个组合可以在时间上对齐，以便在受害者敏感度窗口内引起最大的噪声。
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9.发明授权Multi-phase clock distribution method and system for complex integrated-circuit devices 失效复杂集成电路设备的多相时钟分配方法和系统
公开(公告)号：US5966522A
公开(公告)日：1999-10-12
申请号：US828915
申请日：1997-03-28
CPC分类号： G06F1/10 , G06F17/5077 , H01L27/0207
摘要： A system and method are provided for distributing clock signals within integrated circuitry. The system includes a number of cells for the integrated circuitry such that the cells include substantially horizontal regions within which are disposed substantially horizontal lines representative of a first clock. The cells also include substantially vertical regions within which are disposed vertical lines representative of a second clock. The cells are disposed in substantially horizontal layers. The vertical regions, including the vertical lines representative of a second clock are substantially vertically aligned. The cells include circuitry disposed within each cell such that a first portion of such circuitry includes signal wiring, and a second portion of such circuitry includes clock wiring, and such that the disposition of said circuitry minimizes a cumulative length of signal wiring and clock wiring.
摘要翻译： 提供了用于在集成电路内分配时钟信号的系统和方法。 该系统包括用于集成电路的多个单元，使得单元包括基本上水平的区域，其中基本上水平地布置有代表第一时钟的线。 单元还包括基本上垂直的区域，其中设置了表示第二时钟的垂直线。 电池被设置在大致水平的层中。 包括表示第二时钟的垂直线的垂直区域基本上垂直对齐。 单元包括设置在每个单元内的电路，使得这种电路的第一部分包括信号布线，并且这种电路的第二部分包括时钟布线，并且使得所述电路的布置使信号布线和时钟布线的累积长度最小化。
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10.发明授权
公开(公告)号：US5831870A
公开(公告)日：1998-11-03
申请号：US726722
申请日：1996-10-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and system for characterizing interconnect data within an integrated circuit in order to facilitate parasitic capacitance estimation is disclosed. An integrated circuit typically includes a substrate layer and several metal layers. In accordance with the method and system of the present invention, an overlapping area of interconnect wires is first identified within the integrated circuit. This overlapping area, which is a polygon, may be formed between the substrate layer and at least one interconnect wire in one of the several metal layers. The overlapping area may also be formed between two interconnect wires, each in a different one of the several metal layers. A netname for the overlapping area is then recorded. Finally, a netname of an interconnect wire in a metal layer that is at the same level of an interconnect wire within the overlapping area and an associated distance from each side of the overlapping area is recorded, for every interconnect wire within the overlapping area. By utilizing these recorded information, the parasitic capacitance of the integrated circuit can be estimated more efficiently.
摘要翻译： 公开了一种用于表征集成电路内的互连数据以便于寄生电容估计的方法和系统。 集成电路通常包括基底层和几个金属层。 根据本发明的方法和系统，首先在集成电路内识别互连线的重叠区域。 作为多边形的该重叠区域可以形成在基板层和多个金属层之一中的至少一个互连线之间。 重叠区域也可以形成在两个互连线之间，每个布线在几个金属层中的不同的一个中。 然后记录重叠区域的网络名称。 最后，针对重叠区域内的每个互连线，记录金属层内的互连线的网络名称，该网络位于重叠区域内的互连线的相同电平以及与重叠区域的每一侧相关联的距离。 通过利用这些记录的信息，可以更有效地估计集成电路的寄生电容。
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