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12 条记录 (耗时 0.013 秒)

    Low voltage CMOS differential amplifier
    2.
    发明授权
    Low voltage CMOS differential amplifier 失效
    低电压CMOS差分放大器

    公开(公告)号：US5942940A

    公开(公告)日：1999-08-24

    申请号：US897476

    申请日：1997-07-21

    申请人： Daniel Mark Dreps ,  Byron Lee Krauter ,  Robert Paul Masleid

    发明人： Daniel Mark Dreps ,  Byron Lee Krauter ,  Robert Paul Masleid

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45237 ,  H03F2203/45454

    摘要： A CMOS differential amplifier uses a first pair of complementary MOSFETs and a second pair of complementary MOSFETs coupled to a power supply (by another pair of MOSFETs) in such a manner as to be self-biasing and have improved channel-length modulation characteristics. An N-type MOSFET couples the first and second complementary MOSFET pairs to ground potential via a first resistor, and a P-type MOSFET couples the first and second complementary MOSFET pairs to a power-supply via a second resistor. The first and second resistors can be provided using non-salicided N-type MOSFET resistors. The third N-type MOSFET preferably has a low-threshold voltage, including a zero-threshold voltage, and the substrates of the P-type MOSFETs in the first and second complementary pairs are further preferably connected to the sources of those MOSFETs in order to reduce body-sensitivity effects.

    摘要翻译： CMOS差分放大器使用第一对互补MOSFET和第二对互补MOSFET，其以这样的方式耦合到电源（由另一对MOSFET），并且具有改善的沟道长度调制特性。 N型MOSFET通过第一电阻器将第一和第二互补MOSFET对耦合到地电位，并且P型MOSFET通过第二电阻将第一和第二互补MOSFET对耦合到电源。 第一和第二电阻可以使用非水银N型MOSFET电阻器来提供。 第三N型MOSFET优选地具有包括零阈值电压的低阈值电压，并且第一和第二互补对中的P型MOSFET的衬底进一步优选地连接到这些MOSFET的源极，以便 减少身体敏感性的影响。

    Controllable decoupling capacitor
    3.
    发明授权
    Controllable decoupling capacitor 失效
    可控去耦电容

    公开(公告)号：US5770969A

    公开(公告)日：1998-06-23

    申请号：US518083

    申请日：1995-08-22

    申请人： Lloyd Andre Walls ,  Byron Lee Krauter ,  Stanley Everett Schuster

    发明人： Lloyd Andre Walls ,  Byron Lee Krauter ,  Stanley Everett Schuster

    IPC分类号： G05F3/24 ,  H03K17/16

    CPC分类号： H02H7/16 ,  Y10T307/852

    摘要： A decoupling capacitor and protection circuit is provided that will assist the power supply network in stabilizing the voltage near circuits that demand short rapid transitions in electrical current. The protection circuit also significantly reduces the amount of electrical current drawn by defective large area decoupling capacitors. An inverter stage controls a switching circuit connected in series with a decoupling capacitor. A feedback circuit is provided from the output of the capacitor to the switching circuit. If the capacitor goes bad, then a voltage is present on the feedback circuit and the switching circuit ensures that the output of the failed capacitor is presented with an open circuit so that the short circuit current flow through the capacitor is eliminated. In this manner, the integrity of the other circuits located near the failed capacitor will operate appropriately.

    摘要翻译： 提供去耦电容器和保护电路，其将帮助电源网络稳定电路附近的电压，从而要求电流中的快速快速转换。 保护电路还显着减少了由大面积去耦电容器引起的电流量。 逆变器级控制与去耦电容串联连接的开关电路。 从电容器的输出到开关电路提供反馈电路。 如果电容变坏，则反馈电路上存在电压，开关电路确保故障电容器的输出呈开路状态，从而消除短路电流流过电容器。 以这种方式，位于故障电容器附近的其它电路的完整性将适当地运行。

    Method, system, and product for verifying voltage drop across an entire integrated circuit package
    6.
    发明授权
    Method, system, and product for verifying voltage drop across an entire integrated circuit package 失效
    用于验证整个集成电路封装的电压降的方法，系统和产品

    公开(公告)号：US07134103B2

    公开(公告)日：2006-11-07

    申请号：US10738708

    申请日：2003-12-17

    申请人： Michael Werner Beattie ,  Anirudh Devgan ,  Byron Lee Krauter ,  Hui Zheng

    发明人： Michael Werner Beattie ,  Anirudh Devgan ,  Byron Lee Krauter ,  Hui Zheng

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F2217/40

    摘要： A method, system, and product are disclosed for determining a voltage drop across an entire integrated circuit package. A geometric description of the entire integrated circuit package is determined. The description is subdivided into non-uniform areas. A resistance of each one of the non-uniform areas is determined. A resistive netlist of the entire integrated circuit package is then determined by combining the resistance of each one of the non-uniform areas. The package is then simulated utilizing the netlist to determine the voltage drop across the entire integrated circuit package.

    摘要翻译： 公开了一种用于确定跨整个集成电路封装的电压降的方法，系统和产品。 确定整个集成电路封装的几何描述。 描述细分为非均匀区域。 确定每个不均匀区域的电阻。 然后通过组合每个非均匀区域的电阻来确定整个集成电路封装的电阻网表。 然后使用网表模拟封装以确定整个集成电路封装的电压降。

    Data processing system and method to estimate power in mixed dynamic/static CMOS designs
    7.
    发明授权
    Data processing system and method to estimate power in mixed dynamic/static CMOS designs 失效
    数据处理系统和方法来估计混合动态/静态CMOS设计中的功率

    公开(公告)号：US06338025B1

    公开(公告)日：2002-01-08

    申请号：US09168589

    申请日：1998-10-08

    申请人： Michael Alexander Bowen ,  Byron Lee Krauter ,  Steven Arthur Schmidt ,  Clay Chip Smith ,  Amy May Tuvell

    发明人： Michael Alexander Bowen ,  Byron Lee Krauter ,  Steven Arthur Schmidt ,  Clay Chip Smith ,  Amy May Tuvell

    IPC分类号： G06F1900

    CPC分类号： G06F17/5022

    摘要： An apparatus and method for determining power consumption in logic devices including mixed static and dynamic logic blocks is implemented. Input logical signals are tagged as having dynamical behavior or static behavior, and the power consumption of the logic block determined according to the behavior of the input signal. If an input signal has dynamic behavior, an output signal making a transition in response thereto will make two transitions per clock cycle, and the per cycle power consumption of the logic block is accordingly weighted. In another embodiment, a Boolean behavior signal is calculated for each block from clock phase tags and “one cycle per cycle” circuit level simulations. The per cycle power consumption of each logic block receives a weight in response to the Boolean behavior signal, according the behavior of the block characterized thereby.

    摘要翻译： 实现了包括混合静态和动态逻辑块在内的逻辑设备中的功率消耗的装置和方法。 输入逻辑信号被标记为具有动态行为或静态行为，以及根据输入信号的行为确定的逻辑块的功耗。 如果输入信号具有动态特性，则响应于此的转换的输出信号将在每个时钟周期进行两次转换，并且相应地对逻辑块的每周期功率消耗进行加权。 在另一个实施例中，针对来自时钟相位标签的每个块和“每周期一个周期”电路电平仿真计算布尔行为信号。 根据其特征的块的行为，每个逻辑块的每周期功率消耗响应于布尔行为信号接收权重。

    Digital circuit to measure and/or correct duty cycles
    8.
    发明授权
    Digital circuit to measure and/or correct duty cycles 有权
    用于测量和/或校正占空比的数字电路

    公开(公告)号：US07350095B2

    公开(公告)日：2008-03-25

    申请号：US11082973

    申请日：2005-03-17

    申请人： David William Boerstler ,  Eskinder Hailu ,  Byron Lee Krauter ,  Kazuhiko Miki ,  Jieming Qi

    发明人： David William Boerstler ,  Eskinder Hailu ,  Byron Lee Krauter ,  Kazuhiko Miki ,  Jieming Qi

    IPC分类号： G06F1/00 ,  G06F1/12 ,  G06F1/04

    CPC分类号： G06F1/10 ,  H03K5/1565

    摘要： A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

    摘要翻译： 提供了一种方法，装置和计算机程序来测量和/或校正占空比。 各种信号的占空比，特别是时钟信号是很重要的。 然而，测量非常高频率的信号，芯片外和实验室环境可能是非常困难的并且存在许多问题。 为了解决与片外测量和信号占空比调整相关的问题，可以比较输入信号和分频输入信号，从而便于测量和调整片上信号，包括时钟信号。

    Driving point model utilizing a realizable reduced order circuit for determining a delay of a gate driving an interconnect with inductance
    9.
    发明授权
    Driving point model utilizing a realizable reduced order circuit for determining a delay of a gate driving an interconnect with inductance 失效
    利用可实现的降序电路来确定驱动具有电感的互连的栅极的延迟的驱动点模型

    公开(公告)号：US06496960B1

    公开(公告)日：2002-12-17

    申请号：US09697447

    申请日：2000-10-27

    申请人： Chandramouli V. Kashyap ,  Byron Lee Krauter

    发明人： Chandramouli V. Kashyap ,  Byron Lee Krauter

    IPC分类号： G06F1750

    CPC分类号： G06F17/5036

    摘要： A method for determining an equivalent load at the output of a gate driving an interconnect having resistive, inductive and capacitive elements. The method includes modeling the interconnect utilizing a passive driving point model to derive a realizable reduced order circuit for the interconnect. In an advantageous embodiment, the realizable reduced order circuit includes a first resistance parallel-coupled to an inductance and series-coupled to a pi-model equivalent circuit that includes a second resistance and first and second capacitances.

    摘要翻译： 用于确定驱动具有电阻，电感和电容元件的互连的栅极的输出处的等效负载的方法。 该方法包括使用无源驱动点模型对互连进行建模，以导出互连的可实现的降序电路。 在有利的实施例中，可实现的降序电路包括并联耦合到电感并且串联耦合到包括第二电阻和第一和第二电容的pi模型等效电路的第一电阻。

    Windowing mechanism for reducing pessimism in cross-talk analysis of digital chips
    10.
    发明授权
    Windowing mechanism for reducing pessimism in cross-talk analysis of digital chips 失效
    数字芯片串扰分析中减少悲观的窗口化机制

    公开(公告)号：US06510540B1

    公开(公告)日：2003-01-21

    申请号：US09640540

    申请日：2000-08-17

    申请人： Byron Lee Krauter ,  Sharad Mehrotra ,  Jonathan Humphrey Saxman ,  Paul Gerard Villarrubia ,  David J. Widiger

    发明人： Byron Lee Krauter ,  Sharad Mehrotra ,  Jonathan Humphrey Saxman ,  Paul Gerard Villarrubia ,  David J. Widiger

    IPC分类号： G06F1750

    CPC分类号： G06F17/5036

    摘要： This invention reduces pessimism in cross talk analysis of digital circuits by combining only the peak noises from aggressor nets that can switch simultaneously during the time interval when the downstream receiving latch can sample the errant data. This is done by, first, determining aggressor switching windows and victim sensitivity windows. These windows are then used to determine which combination of noise sources can temporally align so as to cause the greatest noise within the victim sensitivity window.

    摘要翻译： 本发明通过仅在来自下游接收锁存器可以对错误数据进行采样的时间间隔期间同时切换的来自侵略者网络的峰值噪声组合来减少数字电路的串扰分析中的悲观情绪。 这是通过首先确定侵略者切换窗口和受害者敏感性窗口来完成的。 然后，这些窗口用于确定噪声源的哪个组合可以在时间上对齐，以便在受害者敏感度窗口内引起最大的噪声。