公开(公告)号：US20060231895A1

公开(公告)日：2006-10-19

申请号：US11155062

申请日：2005-06-17

申请人： Charvaka Duvvury ,  Gianluca Boselli ,  John Kunz

发明人： Charvaka Duvvury ,  Gianluca Boselli ,  John Kunz

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L29/0619

摘要： A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well, which touches source junction 512c. Source 512 has further an ohmic (silicided) connection to contact 513. A finger-shaped diode (520) with its cathode (521) is located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well (551) positioned between the first n-well and the diode, the third n-well connected to power (Vdd) and approximately perpendicular to the first n-well contact, acting as a guard wall (550).

摘要翻译： 一种用于保护I / O焊盘以防止ESD事件的半导体电路，其包括其源极连接到Vdd和第一n阱的第一n阱（511）中的pMOS晶体管（510），其漏极连接到I / O垫 晶体管具有与第一n阱的指状接触（513），其接触源极结512c。 源512还具有与触点513的欧姆（硅化）连接。 具有其阴极（521）的指状二极管（520）位于第二n阱中并连接到I / O焊盘，并且其阳极连接到地。 阳极位于阴极和第一n阱之间，由此指形阳极和阴极定向成大致垂直于指状晶体管n阱接触。 此外，位于第一n阱和二极管之间的第三指状n阱（551），第三n阱连接到功率（Vdd）并且大致垂直于第一n阱接触，用作保护壁 （550）。

公开(公告)号：US20060231897A1

公开(公告)日：2006-10-19

申请号：US11107033

申请日：2005-04-15

申请人： Charvaka Duvvury ,  Gianluca Boselli ,  John Kunz

发明人： Charvaka Duvvury ,  Gianluca Boselli ,  John Kunz

IPC分类号： H01L29/76

CPC分类号： H01L27/0266 ,  H01L29/0619

摘要： A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well. Further a finger-shaped diode (520) with its cathode (521) located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well (551) positioned between the first n-well and the diode, the third n-well connected to ground and approximately perpendicular to the first n-well contact, acting as a guard wall (550).

摘要翻译： 一种用于保护I / O焊盘以防止ESD事件的半导体电路，其包括其源极连接到Vdd和第一n阱的第一n阱（511）中的pMOS晶体管（510），其漏极连接到I / O垫 晶体管具有到第一n阱的手指形状的接触（513）。 此外，指状二极管（520），其阴极（521）位于第二n阱中并连接到I / O焊盘，并且其阳极连接到地。 阳极位于阴极和第一n阱之间，由此指形阳极和阴极定向成大致垂直于指状晶体管n阱接触。 此外，位于第一n阱和二极管之间的第三指状n阱（551），第三n阱连接到地面并且大致垂直于第一n阱接触，用作保护壁（550） 。

公开(公告)号：US20070284666A1

公开(公告)日：2007-12-13

申请号：US11739801

申请日：2007-04-25

申请人： Charvaka Duvvury ,  Gianluca Boselli

发明人： Charvaka Duvvury ,  Gianluca Boselli

IPC分类号： H01L29/78

CPC分类号： H01L27/0255 ,  H01L27/0292

摘要： A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad (301) against ESD events, when the I/O pad is located between a power pad (303) and a ground potential pad (305a). A first diode (311) and a second diode (312) are connected in series, the anode (311b) of the series connected to the I/O pad and the cathode (312a) connected to the power pad. A third diode (304) has its anode (304b) tied to the ground pad and its cathode (304a) tied to the I/O pad. A string (320) of at least one diode has its anode (321b) connected to the series between the first and second diode (node 313), isolated from the I/O pad, and its cathode (323a) connected to the ground pad. The string (320) may comprise three or more diodes.

摘要翻译： 当所述I / O焊盘位于电源焊盘（303）和接地电位焊盘（305a）之间时，用于局部保护集成电路输入/输出（I / O）焊盘（301）的ESD事件的半导体器件。 第一二极管（311）和第二二极管（312）串联连接，串联的阳极（311b）连接到连接到电源板的I / O焊盘和阴极（312a）。 第三二极管（304）的阳极（304b）连接到接地焊盘，其阴极（304a）连接到I / O焊盘。 至少一个二极管的串（320）具有连接到与I / O焊盘隔离的第一和第二二极管（节点313）之间的串联的阳极（321b），并且其阳极（323a）连接到 接地垫 串（320）可以包括三个或更多个二极管。

公开(公告)号：US20060050453A1

公开(公告)日：2006-03-09

申请号：US10936912

申请日：2004-09-08

申请人： Charvaka Duvvury ,  Gianluca Boselli

发明人： Charvaka Duvvury ,  Gianluca Boselli

IPC分类号： H02H9/00

CPC分类号： H01L27/0255 ,  H01L27/0292

摘要： A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad (301) against ESD events, when the I/O pad is located between a power pad (303) and a ground potential pad (305a). A first diode (311) and a second diode (312) are connected in series, the anode (311b) of the series connected to the I/O pad and the cathode (312a) connected to the power pad. A third diode (304) has its anode (304b) tied to the ground pad and its cathode (304a) tied to the I/O pad. A string (320) of at least one diode has its anode (321b) connected to the series between the first and second diode (node 313), isolated from the I/O pad, and its cathode (323a) connected to the ground pad. The string (320) may comprise three or more diodes.

摘要翻译： 当所述I / O焊盘位于电源焊盘（303）和接地电位焊盘（305a）之间时，用于局部保护集成电路输入/输出（I / O）焊盘（301）的ESD事件的半导体器件。 第一二极管（311）和第二二极管（312）串联连接，串联的阳极（311b）连接到连接到电源板的I / O焊盘和阴极（312a）。 第三二极管（304）的阳极（304b）连接到接地焊盘，其阴极（304a）连接到I / O焊盘。 至少一个二极管的串（320）具有连接到与I / O焊盘隔离的第一和第二二极管（节点313）之间的串联的阳极（321b），并且其阳极（323a）连接到 接地垫 串（320）可以包括三个或更多个二极管。

公开(公告)号：US07282767B2

公开(公告)日：2007-10-16

申请号：US11155062

申请日：2005-06-17

申请人： Charvaka Duvvury ,  Gianluca Boselli ,  John E. Kunz, Jr.

发明人： Charvaka Duvvury ,  Gianluca Boselli ,  John E. Kunz, Jr.

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L29/0619

摘要： A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well, which touches source junction 512c. Source 512 has further an ohmic (silicided) connection to contact 513. A finger-shaped diode (520) with its cathode (521) is located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well (551) positioned between the first n-well and the diode, the third n-well connected to power (Vdd) and approximately perpendicular to the first n-well contact, acting as a guard wall (550).

摘要翻译： 一种用于保护I / O焊盘以防止ESD事件的半导体电路，其包括其源极连接到Vdd和第一n阱的第一n阱（511）中的pMOS晶体管（510），其漏极连接到I / O垫 晶体管具有与第一n阱的指状接触（513），其接触源极结512c。 源512还具有与触点513的欧姆（硅化）连接。 具有其阴极（521）的指状二极管（520）位于第二n阱中并连接到I / O焊盘，并且其阳极连接到地。 阳极位于阴极和第一n阱之间，由此指形阳极和阴极定向成大致垂直于指状晶体管n阱接触。 此外，位于第一n阱和二极管之间的第三指状n阱（551），第三n阱连接到功率（Vdd）并且大致垂直于第一n阱接触，用作保护壁 （550）。

公开(公告)号：US07145204B2

公开(公告)日：2006-12-05

申请号：US11107033

申请日：2005-04-15

申请人： Charvaka Duvvury ,  Gianluca Boselli ,  John E. Kunz, Jr.

发明人： Charvaka Duvvury ,  Gianluca Boselli ,  John E. Kunz, Jr.

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L29/0619

摘要： A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well. Further a finger-shaped diode (520) with its cathode (521) located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well (551) positioned between the first n-well and the diode, the third n-well connected to ground and approximately perpendicular to the first n-well contact, acting as a guard wall (550).

摘要翻译： 一种用于保护I / O焊盘以防止ESD事件的半导体电路，其包括其源极连接到Vdd和第一n阱的第一n阱（511）中的pMOS晶体管（510），其漏极连接到I / O垫 晶体管具有到第一n阱的手指形状的接触（513）。 此外，指状二极管（520），其阴极（521）位于第二n阱中并连接到I / O焊盘，并且其阳极连接到地。 阳极位于阴极和第一n阱之间，由此指形阳极和阴极定向成大致垂直于指状晶体管n阱接触。 此外，位于第一n阱和二极管之间的第三指状n阱（551），第三n阱连接到地面并且大致垂直于第一n阱接触，用作保护壁（550） 。

公开(公告)号：US20110063765A1

公开(公告)日：2011-03-17

申请号：US12951255

申请日：2010-11-22

申请人： Gianluca Boselli ,  Charvaka Duvvury

发明人： Gianluca Boselli ,  Charvaka Duvvury

IPC分类号： H02H9/04

CPC分类号： H01L27/0259

摘要： An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p−layer (38) includes functional circuitry (24) formed on the p−layer (38) including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (24). At least one ESD protection cell (30; in more detail 200) is connected to at least one of the plurality of terminals of the functional circuitry (24). The protection cell includes at least a first Nwell (37) formed in the p− layer (38), a p−doped diffusion (36) within the first Nwell (37) to form at least one Nwell diode comprising an anode (37) and a cathode (36). An NMOS transistor 200 is formed in or on the p− layer (38) comprising a n+ source (43), n+ drain (44) and a channel region comprising a p−region (41) between the source and drain, and a gate electrode (45) on a gate dielectric (46) on the channel region. The terminal of the functional circuit (24, PAD) is coupled to the cathode (36) of the Nwell diode, and the anode (37) of the Nwell diode is connected in series with a path from the drain (44) to the source (43) of the NMOS transistor (200).

摘要翻译： 在包括公共p层（38）的衬底的半导体表面处形成的集成电路（25）包括形成在p层（38）上的功能电路（24），包括多个端子（IN，OUT，I / O）耦合到功能电路（24）。 至少一个ESD保护单元（30;更详细地200）连接到功能电路（24）的多个端子中的至少一个。 保护单元至少包括形成在第一N阱（37）中的p层（38）中的第一N阱（37）和ap掺杂扩散（36），以形成至少一个Nwell二极管，其包括阳极（37）和 阴极（36）。 NMOS晶体管200形成在包括n +源极（43），n +漏极（44）和包括源极和漏极之间的ap区域（41）的沟道区域的p层（38）中或上方，以及栅电极 （45）在沟道区上的栅极电介质（46）上。 功能电路（24，PAD）的端子耦合到Nwell二极管的阴极（36），Nwell二极管的阳极（37）与从漏极（44）到源极 （200）的（43）。

公开(公告)号：US07256460B2

公开(公告)日：2007-08-14

申请号：US11001899

申请日：2004-11-30

申请人： Craig T. Salling ,  Charvaka Duvvury ,  Gianluca Boselli

发明人： Craig T. Salling ,  Charvaka Duvvury ,  Gianluca Boselli

IPC分类号： H01L23/62

CPC分类号： H01L27/0277

摘要： A protection circuit for protecting an integrated circuit pad 201 against an ESD pulse, which comprises a discharge circuit having an elongated MOS transistor 202 (preferably pMOS) in a substrate 205 (preferably n-type), said discharge circuit operable to discharge the ESD pulse to the pad, to ground 203. The embodiment further contains a pump circuit connected to the pad for receiving a portion of the pulse's current; the pump circuit comprises a component 221 determining the size of this current portion (for example, another transistor, a string of forward diodes, or a reverse Zener diode), wherein the component is connected to ground. A discrete resistor 222 (for example about 40 to 60Ω) is connected between the pad and the component and is operable to generate a voltage drop (about 0.5 to 1.0 V) by the current portion. A plurality of contacts to the substrate connects to the resistor so that the voltage drop is uniformly impressed on the substrate to ensure uniform turn-on of the elongated transistor for uniform pulse discharge.

摘要翻译： 一种用于保护集成电路焊盘201抵抗ESD脉冲的保护电路，其包括在衬底205（优选为n型）中具有细长MOS晶体管202（优选为pMOS）的放电电路，所述放电电路可操作以将ESD脉冲 到垫子，到地面203。 该实施例还包括连接到焊盘的泵电路，用于接收脉冲电流的一部分; 泵电路包括确定该电流部分（例如，另一晶体管，一串正向二极管或反向齐纳二极管）的尺寸的部件221，其中部件连接到地。 分立电阻器222（例如约40至60Omega）连接在焊盘和部件之间，并且可操作以通过电流部分产生电压降（约0.5至1.0V）。 与衬底的多个触点连接到电阻器，使得电压降均匀地施加在衬底上，以确保用于均匀脉冲放电的细长晶体管的均匀导通。

公开(公告)号：US07838924B2

公开(公告)日：2010-11-23

申请号：US12108230

申请日：2008-04-23

申请人： Gianluca Boselli ,  Charvaka Duvvury

发明人： Gianluca Boselli ,  Charvaka Duvvury

IPC分类号： H01L23/62

CPC分类号： H01L27/0259

摘要： An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p-layer (38) includes functional circuitry (24) formed on the p-layer (38) including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (24). At least one ESD protection cell (30; in more detail 200) is connected to at least one of the plurality of terminals of the functional circuitry (24). The protection cell includes at least a first Nwell (37) formed in the p-layer (38), a p-doped diffusion (36) within the first Nwell (37) to form at least one Nwell diode comprising an anode (37) and a cathode (36). An NMOS transistor 200 is formed in or on the p-layer (38) comprising a n+ source (43), n+drain (44) and a channel region comprising a p-region (41) between the source and drain, and a gate electrode (45) on a gate dielectric (46) on the channel region. The terminal of the functional circuit (24, PAD) is coupled to the cathode (36) of the Nwell diode, and the anode (37) of the Nwell diode is connected in series with a path from the drain (44) to the source (43) of the NMOS transistor (200).

摘要翻译： 在包括公共p层（38）的衬底的半导体表面处形成的集成电路（25）包括形成在p层（38）上的功能电路（24），包括多个端子（IN，OUT，I / O）耦合到功能电路（24）。 至少一个ESD保护单元（30;更详细地200）连接到功能电路（24）的多个端子中的至少一个。 保护单元包括至少形成在p层（38）中的第一N阱（37），在第一N阱（37）内的p掺杂扩散层（36），以形成至少一个包含阳极（37）的Nwell二极管， 和阴极（36）。 NMOS晶体管200形成在包括n +源极（43），n +漏极（44）和包括源极和漏极之间的p区域（41）的沟道区域的p层（38）中或上，以及 栅电极（45）在沟道区上的栅极电介质（46）上。 功能电路（24，PAD）的端子耦合到Nwell二极管的阴极（36），Nwell二极管的阳极（37）与从漏极（44）到源极 （200）的（43）。

公开(公告)号：US07277263B2

公开(公告)日：2007-10-02

申请号：US10936912

申请日：2004-09-08

申请人： Charvaka Duvvury ,  Gianluca Boselli

发明人： Charvaka Duvvury ,  Gianluca Boselli

IPC分类号： H02H9/00

CPC分类号： H01L27/0255 ,  H01L27/0292

摘要： A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad (301) against ESD events, when the I/O pad is located between a power pad (303) and a ground potential pad (305a). A first diode (311) and a second diode (312) are connected in series, the anode (311b) of the series connected to the I/O pad and the cathode (312a) connected to the power pad. A third diode (304) has its anode (304b) tied to the ground pad and its cathode (304a) tied to the I/O pad. A string (320) of at least one diode has its anode (321b) connected to the series between the first and second diode (node 313), isolated from the I/O pad, and its cathode (323a) connected to the ground pad. The string (320) may comprise three or more diodes.

摘要翻译： 当所述I / O焊盘位于电源焊盘（303）和接地电位焊盘（305a）之间时，用于局部保护集成电路输入/输出（I / O）焊盘（301）的ESD事件的半导体器件。 第一二极管（311）和第二二极管（312）串联连接，串联的阳极（311b）连接到连接到电源板的I / O焊盘和阴极（312a）。 第三二极管（304）的阳极（304b）连接到接地焊盘，其阴极（304a）连接到I / O焊盘。 至少一个二极管的串（320）具有连接到与I / O焊盘隔离的第一和第二二极管（节点313）之间的串联的阳极（321b），并且其阳极（323a）连接到 接地垫 串（320）可以包括三个或更多个二极管。