公开(公告)号：US06372619B1

公开(公告)日：2002-04-16

申请号：US09918085

申请日：2001-07-30

申请人： Chender Huang ,  Pei-Hwa Tsao

发明人： Chender Huang ,  Pei-Hwa Tsao

IPC分类号： H01L2128

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method for fabricating a wafer level chip scale package with discrete package encapsulation and devices formed by the method are described. A dry film photoresist layer is first deposited on top of a pre-processed wafer complete with a plurality of bond pads and an I/O redistribution metal layer. The dry film photoresist layer is then patterned to form a plurality of trench openings and a plurality of via openings followed by the process of depositing a liquid photoresist material into the plurality of trench openings and plating a conductive metal into the plurality of via openings to form via plugs. After the dry film photoresist layer is removed, an encapsulant layer is printed on top of the wafer to embed the protrusions formed by the liquid photoresist material and the via plugs.

摘要翻译： 描述了利用分立封装封装制造晶片级芯片级封装的方法，以及通过该方法形成的器件。 首先将干膜光致抗蚀剂层沉积在具有多个接合焊盘和I / O再分布金属层的预处理晶片的顶部上。 然后将干膜光致抗蚀剂层图案化以形成多个沟槽开口和多个通孔开口，随后将液态光致抗蚀剂材料沉积到多个沟槽开口中并将导电金属镀覆到多个通孔开口中以形成 通过插头。 在去除干膜光致抗蚀剂层之后，将密封剂层印刷在晶片的顶部上以嵌入由液态光致抗蚀剂材料和通孔塞形成的突起。

公开(公告)号：US07154185B2

公开(公告)日：2006-12-26

申请号：US10718191

申请日：2003-11-20

申请人： Hsin-Hui Lee ,  Pei-Hwa Tsao ,  Chao-Yuan Su

发明人： Hsin-Hui Lee ,  Pei-Hwa Tsao ,  Chao-Yuan Su

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/562 ,  H01L23/16 ,  H01L23/3128 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for encapsulating an integrated circuit chip is described. An intergrated circuit chip is attached to a substrate; a stress buffering material only covers corners of the integrated circuit chip; and an encapsulation material coats the integated circuit chip and a portion of the substrate.

摘要翻译： 描述了一种用于封装集成电路芯片的方法。 集成电路芯片附着在基板上; 应力缓冲材料仅覆盖集成电路芯片的角部; 并且封装材料涂覆整体电路芯片和衬底的一部分。

公开(公告)号：US20050112795A1

公开(公告)日：2005-05-26

申请号：US10718191

申请日：2003-11-20

申请人： Hsin-Hui Lee ,  Pei-Hwa Tsao ,  Chao-Yuan Su

发明人： Hsin-Hui Lee ,  Pei-Hwa Tsao ,  Chao-Yuan Su

IPC分类号： H01L21/44 ,  H01L21/50 ,  H01L21/56 ,  H01L21/58 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31

CPC分类号： H01L23/562 ,  H01L23/16 ,  H01L23/3128 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for encapsulating an integrated circuit chip is described. An integrated circuit chip is attached to a substrate. A dam is formed surrounding the integrated circuit chip. At least one corner of the integrated circuit chip is covered with a stress buffering material. The integrated circuit chip and all of the substrate within the dam are coated with an encapsulation material wherein the encapsulation material covers the stress buffering material and wherein the stress buffering material prevents delamination of the encapsulation material at the corners of the integrated circuit chip.

摘要翻译： 描述了一种用于封装集成电路芯片的方法。 集成电路芯片附着在基板上。 围绕集成电路芯片形成一个坝。 集成电路芯片的至少一个角部被应力缓冲材料覆盖。 集成电路芯片和坝内的所有衬底都涂覆有封装材料，其中封装材料覆盖应力缓冲材料，并且其中应力缓冲材料防止封装材料在集成电路芯片的拐角处的分层。