公开(公告)号：US08305831B2

公开(公告)日：2012-11-06

申请号：US12885826

申请日：2010-09-20

申请人： Cheng Hung Lee ,  Chung-Yi Wu ,  Hsu-Shun Chen ,  Chung-Ji Lu

发明人： Cheng Hung Lee ,  Chung-Yi Wu ,  Hsu-Shun Chen ,  Chung-Ji Lu

IPC分类号： G11C5/14

CPC分类号： G11C11/413

摘要： An SRAM includes circuitry configured for the SRAM to operate at different operation modes using different voltage levels wherein the voltage level and thus the supply current leakage is regulated based on the operation mode. For example, the SRAM, in a normal operation mode, consumes power as other SRAMs. In a deep sleep mode the supply voltage (e.g., VDDI) for the bit cell in the SRAM macro is lowered by about 20-40% of the SRAM supply voltage (e.g., VDD), sufficient to retain the data in the bit cell. When access to the SRAM is not needed, the SRAM operates in the sleep mode, consuming little or no power.

摘要翻译： SRAM包括被配置用于使用不同的电压电平在不同的操作模式下工作的电路，其中基于操作模式调节电压电平和因此的电流泄漏。 例如，在正常工作模式下，SRAM将作为其他SRAM消耗电力。 在深度睡眠模式下，SRAM宏中的位单元的电源电压（例如，VDDI）降低SRAM电源电压（例如VDD）的约20-40％，足以将数据保留在位单元中。 当不需要访问SRAM时，SRAM在睡眠模式下运行，消耗很少或没有电源。

公开(公告)号：US08451669B2

公开(公告)日：2013-05-28

申请号：US13443619

申请日：2012-04-10

申请人： Hsu-Shun Chen ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Chih-Chieh Chiu

发明人： Hsu-Shun Chen ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Chih-Chieh Chiu

IPC分类号： G11C7/00

CPC分类号： G11C7/1048 ,  G11C5/14

摘要： In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.

摘要翻译： 在与存储器阵列相关的一些实施例中，读出放大器（SA）使用第一电源，例如电压VDDA，而其它电路（例如，信号输出逻辑）使用第二电源，例如电压VDDB。 各种实施例将SA和一对传送装置放置在本地IO行上，并将电压保持器放置在同一存储器阵列的主IO部分。 SA，传输装置和电压保持器在适当的情况下一起工作，使得由电压VDDB提供的电路的数据逻辑与由电压VDDA提供的电路的数据逻辑相同。

公开(公告)号：US20110158007A1

公开(公告)日：2011-06-30

申请号：US12708923

申请日：2010-02-19

申请人： Hsu-Shun Chen ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Chih-Chieh Chiu

发明人： Hsu-Shun Chen ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Chih-Chieh Chiu

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C7/1048 ,  G11C5/14

摘要： In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.

摘要翻译： 在与存储器阵列相关的一些实施例中，读出放大器（SA）使用第一电源，例如电压VDDA，而其它电路（例如，信号输出逻辑）使用第二电源，例如电压VDDB。 各种实施例将SA和一对传送装置放置在本地IO行上，并将电压保持器放置在同一存储器阵列的主IO部分。 SA，传输装置和电压保持器在适当的情况下一起工作，使得由电压VDDB提供的电路的数据逻辑与由电压VDDA提供的电路的数据逻辑相同。

公开(公告)号：US08174911B2

公开(公告)日：2012-05-08

申请号：US12708923

申请日：2010-02-19

申请人： Hsu-Shun Chen ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Chih-Chieh Chiu

发明人： Hsu-Shun Chen ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Chih-Chieh Chiu

IPC分类号： G11C7/00

CPC分类号： G11C7/1048 ,  G11C5/14

摘要： In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.

摘要翻译： 在与存储器阵列相关的一些实施例中，读出放大器（SA）使用第一电源，例如电压VDDA，而其它电路（例如，信号输出逻辑）使用第二电源，例如电压VDDB。 各种实施例将SA和一对传送装置放置在本地IO行上，并将电压保持器放置在同一存储器阵列的主IO部分。 SA，传输装置和电压保持器在适当的情况下一起工作，使得由电压VDDB提供的电路的数据逻辑与由电压VDDA提供的电路的数据逻辑相同。

公开(公告)号：US08427888B2

公开(公告)日：2013-04-23

申请号：US12702594

申请日：2010-02-09

申请人： Chung-Ji Lu ,  Lee-Cheng Hung ,  Hung-Jen Liao ,  Hsu-Shun Chen ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Uppu Sharath Chandra

发明人： Chung-Ji Lu ,  Lee-Cheng Hung ,  Hung-Jen Liao ,  Hsu-Shun Chen ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Uppu Sharath Chandra

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C8/10

摘要： A representative circuit device includes a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from a first voltage level to a second voltage level, providing a level shifted first address signal; and a word-line driver having at least one input for receiving a plurality of address signals, wherein the at least one input includes a first input that is coupled to the local control circuit to receive the level shifted first address signal, and an output that is electrically coupled to a word line of a memory cell array.

摘要翻译： 代表性电路装置包括具有电平移位器的本地控制电路，其中响应于接收到第一地址信号，电平移位器将第一地址信号从第一电压电平移位到第二电压电平，提供电平移位的第一地址信号 ; 以及具有用于接收多个地址信号的至少一个输入的字线驱动器，其中所述至少一个输入包括耦合到所述本地控制电路以接收所述电平移位的第一地址信号的第一输入，以及输出， 电耦合到存储单元阵列的字线。

公开(公告)号：US08355277B2

公开(公告)日：2013-01-15

申请号：US13008992

申请日：2011-01-19

申请人： Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Hsu-Shun Chen ,  Chung-Ji Lu ,  Cheng Hung Lee ,  Hung-Jen Liao

发明人： Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Hsu-Shun Chen ,  Chung-Ji Lu ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC分类号： G11C11/413 ,  G11C5/14

CPC分类号： G11C11/413

摘要： A SRAM system includes: a SRAM cell array coupled between high and low supply nodes, a difference therebetween defining a data retention voltage (VDR) for a low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply and disconnecting the one high and low supply nodes from the main power supply during the low power data retention mode; a monitor cell including a SRAM cell preloaded with a data bit and configured for data destruction responsive to a reduction in VDR before data destruction occurs in the SRAM cell array; and a clamping power switch responsive to data destruction in the monitor cell to couple the one of the high and low supply nodes to the main power supply.

摘要翻译： SRAM系统包括：耦合在高电源节点和低电源节点之间的SRAM单元阵列，其间限定用于低功率数据保持模式的数据保持电压（VDR）; 主电源开关将高电源和低电源节点之一耦合到主电源，并且在低功率数据保持模式期间将一个高电源和低电源节点与主电源断开; 监控单元，其包括预先装载有数据位的SRAM单元，并且被配置为在SRAM单元阵列中发生数据破坏之前响应于VDR的减小而进行的数据破坏; 以及钳位电源开关，其响应于监视器单元中的数据破坏，将高电源节点和低电源节点中的一个耦合到主电源。

公开(公告)号：US20130003446A1

公开(公告)日：2013-01-03

申请号：US13616377

申请日：2012-09-14

申请人： Hsu-Shun Chen ,  Cheng-Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

发明人： Hsu-Shun Chen ,  Cheng-Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

IPC分类号： G11C5/14 ,  G11C11/00

CPC分类号： G11C8/08 ,  G11C11/413

摘要： An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current.

摘要翻译： 集成电路包括正电源节点，电流跟踪电路和包括并联耦合的多个电流路径的电流镜像电路。 多个电流通路的电流反映了电流跟踪电路的电流。 电流镜像电路被配置为响应于正电源节点上的正电源电压的减小而逐个关闭多个电流路径。 集成电路还包括接收多个电流路径的求和电流的充电节点，其中充电节点上的电压被配置为通过对和电流的充电而增加。

公开(公告)号：US08279684B2

公开(公告)日：2012-10-02

申请号：US12842189

申请日：2010-07-23

申请人： Hsu-Shun Chen ,  Cheng Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

发明人： Hsu-Shun Chen ,  Cheng Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C11/413

摘要： An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current.

摘要翻译： 集成电路包括正电源节点，电流跟踪电路和包括并联耦合的多个电流路径的电流镜像电路。 多个电流通路的电流反映了电流跟踪电路的电流。 电流镜像电路被配置为响应于正电源节点上的正电源电压的减小而逐个关闭多个电流路径。 集成电路还包括接收多个电流路径的求和电流的充电节点，其中充电节点上的电压被配置为通过对和电流的充电而增加。

公开(公告)号：US09099168B2

公开(公告)日：2015-08-04

申请号：US13616377

申请日：2012-09-14

申请人： Hsu-Shun Chen ,  Cheng-Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

发明人： Hsu-Shun Chen ,  Cheng-Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

IPC分类号： G11C8/08 ,  G11C11/413

CPC分类号： G11C8/08 ,  G11C11/413

摘要： An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current.

摘要翻译： 集成电路包括正电源节点，电流跟踪电路和包括并联耦合的多个电流路径的电流镜像电路。 多个电流通路的电流反映了电流跟踪电路的电流。 电流镜像电路被配置为响应于正电源节点上的正电源电压的减小而逐个关闭多个电流路径。 集成电路还包括接收多个电流路径的求和电流的充电节点，其中充电节点上的电压被配置为通过对和电流的充电而增加。

公开(公告)号：US20110085399A1

公开(公告)日：2011-04-14

申请号：US12842189

申请日：2010-07-23

申请人： Hsu-Shun Chen ,  Cheng Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

发明人： Hsu-Shun Chen ,  Cheng Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

IPC分类号： G11C5/14

CPC分类号： G11C8/08 ,  G11C11/413

摘要： An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current.

摘要翻译： 集成电路包括正电源节点，电流跟踪电路和包括并联耦合的多个电流路径的电流镜像电路。 多个电流通路的电流反映了电流跟踪电路的电流。 电流镜像电路被配置为响应于正电源节点上的正电源电压的减小而逐个关闭多个电流路径。 集成电路还包括接收多个电流路径的求和电流的充电节点，其中充电节点上的电压被配置为通过对和电流的充电而增加。