公开(公告)号：US08355277B2

公开(公告)日：2013-01-15

申请号：US13008992

申请日：2011-01-19

申请人： Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Hsu-Shun Chen ,  Chung-Ji Lu ,  Cheng Hung Lee ,  Hung-Jen Liao

发明人： Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Hsu-Shun Chen ,  Chung-Ji Lu ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC分类号： G11C11/413 ,  G11C5/14

CPC分类号： G11C11/413

摘要： A SRAM system includes: a SRAM cell array coupled between high and low supply nodes, a difference therebetween defining a data retention voltage (VDR) for a low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply and disconnecting the one high and low supply nodes from the main power supply during the low power data retention mode; a monitor cell including a SRAM cell preloaded with a data bit and configured for data destruction responsive to a reduction in VDR before data destruction occurs in the SRAM cell array; and a clamping power switch responsive to data destruction in the monitor cell to couple the one of the high and low supply nodes to the main power supply.

摘要翻译： SRAM系统包括：耦合在高电源节点和低电源节点之间的SRAM单元阵列，其间限定用于低功率数据保持模式的数据保持电压（VDR）; 主电源开关将高电源和低电源节点之一耦合到主电源，并且在低功率数据保持模式期间将一个高电源和低电源节点与主电源断开; 监控单元，其包括预先装载有数据位的SRAM单元，并且被配置为在SRAM单元阵列中发生数据破坏之前响应于VDR的减小而进行的数据破坏; 以及钳位电源开关，其响应于监视器单元中的数据破坏，将高电源节点和低电源节点中的一个耦合到主电源。

公开(公告)号：US08427888B2

公开(公告)日：2013-04-23

申请号：US12702594

申请日：2010-02-09

申请人： Chung-Ji Lu ,  Lee-Cheng Hung ,  Hung-Jen Liao ,  Hsu-Shun Chen ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Uppu Sharath Chandra

发明人： Chung-Ji Lu ,  Lee-Cheng Hung ,  Hung-Jen Liao ,  Hsu-Shun Chen ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Uppu Sharath Chandra

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C8/10

摘要： A representative circuit device includes a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from a first voltage level to a second voltage level, providing a level shifted first address signal; and a word-line driver having at least one input for receiving a plurality of address signals, wherein the at least one input includes a first input that is coupled to the local control circuit to receive the level shifted first address signal, and an output that is electrically coupled to a word line of a memory cell array.

摘要翻译： 代表性电路装置包括具有电平移位器的本地控制电路，其中响应于接收到第一地址信号，电平移位器将第一地址信号从第一电压电平移位到第二电压电平，提供电平移位的第一地址信号 ; 以及具有用于接收多个地址信号的至少一个输入的字线驱动器，其中所述至少一个输入包括耦合到所述本地控制电路以接收所述电平移位的第一地址信号的第一输入，以及输出， 电耦合到存储单元阵列的字线。

公开(公告)号：US08792292B2

公开(公告)日：2014-07-29

申请号：US13046625

申请日：2011-03-11

申请人： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chung-Ji Lu ,  Derek C. Tao ,  Cheng Hung Lee ,  Hung-Jen Liao

发明人： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chung-Ji Lu ,  Derek C. Tao ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC分类号： G11C29/00

CPC分类号： G11C29/846

摘要： A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.

摘要翻译： 电路包括被配置为存储第一行地址的故障地址寄存器，耦合到故障地址寄存器的行地址修改器，其中行地址修改器被配置为修改从故障地址寄存器接收的第一行地址以生成第二行 地址。 第一比较器被配置为接收和比较第一行地址和第三行地址。 第二比较器被配置为接收和比较第二行地址和第三行地址。 第一行地址和第二行地址是存储器中的失败行地址。

公开(公告)号：US20120230127A1

公开(公告)日：2012-09-13

申请号：US13046625

申请日：2011-03-11

申请人： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chung-Ji Lu ,  Derek C. Tao ,  Cheng Hung Lee ,  Hung-Jen Liao

发明人： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chung-Ji Lu ,  Derek C. Tao ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC分类号： G11C29/04

CPC分类号： G11C29/846

摘要： A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.

摘要翻译： 电路包括被配置为存储第一行地址的故障地址寄存器，耦合到故障地址寄存器的行地址修改器，其中行地址修改器被配置为修改从故障地址寄存器接收的第一行地址以生成第二行 地址。 第一比较器被配置为接收和比较第一行地址和第三行地址。 第二比较器被配置为接收和比较第二行地址和第三行地址。 第一行地址和第二行地址是存储器中的失败行地址。

公开(公告)号：US20120020176A1

公开(公告)日：2012-01-26

申请号：US12839575

申请日：2010-07-20

申请人： Chung-Ji Lu ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Derek C. Tao ,  Annie-Li-Keow Lum ,  Hong-Chen Cheng

发明人： Chung-Ji Lu ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Derek C. Tao ,  Annie-Li-Keow Lum ,  Hong-Chen Cheng

IPC分类号： G11C7/06 ,  H03F3/45

CPC分类号： G11C7/067 ,  G11C7/065

摘要： Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain.

摘要翻译： 一些实施例涉及一种电路，包括：具有第一左漏极，第一左栅极和第一左源的第一左晶体管; 第二左晶体管，具有第二左漏极，第二左栅极和第二左源极; 第三左晶体管，具有第三左漏极，第三左栅极和第三左源; 第一右晶体管，具有第一右漏极，第一右栅极和第一右源; 第二右晶体管，具有第二右漏极，第二右栅极和第二右源; 第三右晶体管，具有第三右漏极，第三右栅极和第三右源; 左节点，电耦合第一左排水口，第二左排水管，第二左闸门，第三右闸门和第三左排水管; 以及电连接第一右排水管，第二右排水管，第二右浇口，第三左浇口和第三右排水沟的右节点。

公开(公告)号：US08942053B2

公开(公告)日：2015-01-27

申请号：US13535075

申请日：2012-06-27

申请人： Chung-Ji Lu ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Derek C. Tao ,  Annie-Li-Keow Lum ,  Hong-Chen Cheng

发明人： Chung-Ji Lu ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Derek C. Tao ,  Annie-Li-Keow Lum ,  Hong-Chen Cheng

IPC分类号： G11C7/02 ,  G11C7/06

CPC分类号： G11C7/067 ,  G11C7/065

摘要： A circuit includes a first node, a second node, a first current mirror circuit, and a second current mirror circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current mirror circuit is coupled to the first node, and the mirrored end of the first current mirror circuit is coupled to the second node. The second current mirror circuit has a reference end and a mirrored end. The reference end of the second current mirror circuit is coupled to the second node, and the mirrored end of the second current mirror circuit is coupled to the first node.

摘要翻译： 电路包括第一节点，第二节点，第一电流镜电路和第二电流镜电路。 第一电流镜电路具有参考端和镜像端。 第一电流镜电路的参考端耦合到第一节点，并且第一电流镜电路的镜像端耦合到第二节点。 第二电流镜电路具有参考端和镜像端。 第二电流镜电路的参考端耦合到第二节点，并且第二电流镜电路的镜像端耦合到第一节点。

公开(公告)号：US08223571B2

公开(公告)日：2012-07-17

申请号：US12839575

申请日：2010-07-20

申请人： Chung-Ji Lu ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Derek C. Tao ,  Annie-Li-Keow Lum ,  Hong-Chen Cheng

发明人： Chung-Ji Lu ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Derek C. Tao ,  Annie-Li-Keow Lum ,  Hong-Chen Cheng

IPC分类号： G11C7/02

CPC分类号： G11C7/067 ,  G11C7/065

摘要： A circuit includes a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain.

摘要翻译： 电路包括具有第一左漏极，第一左栅极和第一左源的第一左晶体管; 第二左晶体管，具有第二左漏极，第二左栅极和第二左源极; 第三左晶体管，具有第三左漏极，第三左栅极和第三左源; 第一右晶体管，具有第一右漏极，第一右栅极和第一右源; 第二右晶体管，具有第二右漏极，第二右栅极和第二右源; 第三右晶体管，具有第三右漏极，第三右栅极和第三右源; 左节点，电耦合第一左排水口，第二左排水管，第二左闸门，第三右闸门和第三左排水管; 以及电连接第一右排水管，第二右排水管，第二右浇口，第三左浇口和第三右排水沟的右节点。

公开(公告)号：US20130094307A1

公开(公告)日：2013-04-18

申请号：US13271353

申请日：2011-10-12

申请人： Hong-Chen CHENG ,  Jung-Ping Yang ,  Chiting Cheng ,  Cheng-Hung Lee ,  Sang H. Dong ,  Hung-Jen Liao

发明人： Hong-Chen CHENG ,  Jung-Ping Yang ,  Chiting Cheng ,  Cheng-Hung Lee ,  Sang H. Dong ,  Hung-Jen Liao

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C11/419

摘要： In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV.

摘要翻译： 在具有耦合到字线和位线的位单元阵列的数字存储器中，每个位单元具有通过将栅极晶体管直接寻址而与位线隔离的交叉耦合的反相器，部分或全部位单元可在睡眠模式和 响应于控制信号的待机模式。 位线偏置电路控制在处于睡眠模式时使位线浮动的电压。 用于互补对中的每个位线BL或BLB的上拉晶体管具有耦合到正电源电压的导电沟道和耦合到该对BLB或BL中的另一位线的栅极。 连接晶体管也可以耦合在互补对的位线之间，使浮置位线降低到差值ΔVV的电源电压。

公开(公告)号：US07848174B2

公开(公告)日：2010-12-07

申请号：US12126780

申请日：2008-05-23

申请人： Hong-Chen Cheng ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Ruei-Je Tsai

发明人： Hong-Chen Cheng ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Ruei-Je Tsai

IPC分类号： G11C8/00 ,  G11C7/00

CPC分类号： G11C11/18 ,  G11C11/413

摘要： A word-line tracking system for a memory array having a plurality of memory cells, the word-line tracking system comprises a dummy row having substantially identical structure as one or more regular rows of the memory cells, the dummy row including a dummy word-line having a first and a second end at the opposite longitudinal ends of the dummy word-line, the first end being connected to a word-line driver, a self timing generator configured to receive a clock signal and generate a pulse signal in sync with the clock signal for the dummy word-line driver, the self timing generator having a first terminal for receiving a feedback signal to determine the falling edge of the pulse signal, a voltage-to-current converter connected to the second end of the dummy word-line, a current-to-voltage converter connected to the feedback terminal, and a wire connecting the voltage-to-current converter to the current-to-voltage converter.

摘要翻译： 一种用于具有多个存储单元的存储器阵列的字线跟踪系统，该字线跟踪系统包括具有与存储器单元的一个或多个规则行基本相同结构的虚拟行，该虚拟行包括一个虚拟字 - 所述线在所述虚拟字线的相对的纵向端具有第一端和第二端，所述第一端连接到字线驱动器，自定时发生器被配置为接收时钟信号并与 用于虚拟字线驱动器的时钟信号，自定时发生器具有用于接收反馈信号以确定脉冲信号的下降沿的第一端子，连接到虚拟字的第二端的电压 - 电流转换器 线路，连接到反馈端子的电流 - 电压转换器以及将电压 - 电流转换器连接到电流 - 电压转换器的导线。

公开(公告)号：US08675439B2

公开(公告)日：2014-03-18

申请号：US13271353

申请日：2011-10-12

申请人： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chiting Cheng ,  Cheng-Hung Lee ,  Sang H. Dong ,  Hung-Jen Liao

发明人： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chiting Cheng ,  Cheng-Hung Lee ,  Sang H. Dong ,  Hung-Jen Liao

IPC分类号： G11C5/14

CPC分类号： G11C7/12 ,  G11C11/419

摘要： In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV.

摘要翻译： 在具有耦合到字线和位线的位单元阵列的数字存储器中，每个位单元具有通过将栅极晶体管直接寻址而与位线隔离的交叉耦合的反相器，部分或全部位单元可在睡眠模式和 响应于控制信号的待机模式。 位线偏置电路控制在处于睡眠模式时使位线浮动的电压。 用于互补对中的每个位线BL或BLB的上拉晶体管具有耦合到正电源电压的导电沟道和耦合到该对BLB或BL中的另一位线的栅极。 连接晶体管也可以耦合在互补对的位线之间，使浮置位线降低到差值ΔVV的电源电压。