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公开(公告)号：US20240297173A1
公开(公告)日：2024-09-05
申请号：US17795887
申请日：2021-09-18
发明人： Hui LU , Yipeng CHEN , Shuai XIE , Fei FANG , Shuo LI , Xuewei TIAN , Ling SHI
IPC分类号： H01L27/12 , G09G3/3233 , H10K59/131
CPC分类号： H01L27/1225 , G09G3/3233 , H01L27/124 , H01L27/127 , H10K59/131 , G09G2300/0426 , G09G2300/0465 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/08 , G09G2320/0233 , G09G2320/0247 , G09G2330/021
摘要： A display substrate, a manufacturing method therefor, and a display apparatus are provided. The display substrate includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on an substrate. The first semiconductor layer includes active layers of a plurality of poly silicon transistors, the first conductive layer includes gates of a plurality of poly silicon transistors, a first electrode plate of a storage capacitor and a first scan signal line. The second conductive layer includes a second electrode plate of the storage capacitor. The second semiconductor layer includes active layers of a plurality of oxide transistors. The third conductive layer includes gates of the plurality of oxide transistors.
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公开(公告)号：US20240265873A1
公开(公告)日：2024-08-08
申请号：US18020971
申请日：2022-01-29
发明人： Yipeng CHEN , Hui LU , Ling SHI
IPC分类号： G09G3/3266 , G11C19/28 , H01L27/12
CPC分类号： G09G3/3266 , G11C19/287 , H01L27/1225 , H01L27/1229 , H01L27/124 , H01L27/1259 , G09G2300/0426 , G09G2300/0819 , G09G2300/0861 , G09G2310/0286 , G09G2310/08 , G09G2320/045 , G09G2330/02
摘要： A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a gate driving circuit including shift register units and clock signal lines including a first clock signal line, a second clock signal line providing a second clock signal, and a third clock signal line providing a third clock signal. An input circuit of a n-th stage shift register unit in the shift register units is connected with the first clock signal line, a first control circuit of the n-th stage shift register unit is connected with the first clock signal line, the second clock signal line, and the third clock signal line, a second control circuit of the n-th stage shift register unit is connected with the second clock signal line, and a phase of the second clock signal is opposite to a phase of the third clock signal.
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公开(公告)号：US20230269985A1
公开(公告)日：2023-08-24
申请号：US17922508
申请日：2021-11-19
发明人： Yipeng CHEN , Ling SHI , Ke LIU , Hui LU
IPC分类号： H10K59/35 , H10K59/131
CPC分类号： H10K59/353 , H10K59/131
摘要： The present disclosure relates to the field of display technology, and provides a display panel and a display device. The display panel includes a first display area and a second display area, and further includes a plurality of first pixel islands. The first pixel islands are in the first display area and include: at least one first light-emitting unit; at least one first pixel driving circuit, arranged in a one-to-one correspondence with the at least one first light-emitting unit, and configured to provide a driving current to a first light-emitting unit corresponding thereto; and a plurality of first signal line segments configured to provide signals to the at least one first pixel driving circuit.
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4.发明公开公开(公告)号：US20240203316A1
公开(公告)日：2024-06-20
申请号：US17910539
申请日：2021-10-25
发明人： Zhu WANG , Zhenglong YAN , Hui LU , Ke LIU , Ling SHI , Yipeng CHEN
CPC分类号： G09G3/2092 , G09G2310/0286 , G09G2310/08 , G11C19/28
摘要： The present disclosure provides a shift register unit and a driving method therefor, a gate drive circuit, and a display device, belonging to the field of display technologies. In the shift register unit, a first input circuit can control a potential of a first node under control of a first clock signal provided by a first clock terminal and control a potential of a third node under control of a potential of a second node. A second input circuit can control the potential of the second node under control of the first clock signal, an input control signal provided by an input control terminal, the potential of the third node, and the potential of the first node. An output circuit can transmit a pull-up power signal at a high potential or a pull-down power signal at a low potential to an output terminal under control of the third node. In this way, the potential of the output terminal can be reliably controlled only by flexibly setting clock signals provided by two clock terminals and the input control signal provided by the input control terminal. The control process is simple, and the control flexibility is high.
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公开(公告)号：US20230093654A1
公开(公告)日：2023-03-23
申请号：US17785742
申请日：2021-09-14
发明人： Wenqiang LI , Chuntong JIANG , Ling SHI , Yipeng CHEN , Shuai XIE
IPC分类号： G09G3/20
摘要： The present disclosure provides a gate driving unit, a gate driving method, a gate driving circuit and a display device. The gate driving unit includes a first clock signal end, a second clock signal end, a third clock signal end, a fourth clock signal end, a first output node control circuitry, a second output node control circuitry, a first control node control circuitry and an output circuitry. According to the present disclosure, it is able to provide a gate driving signal for an N-type transistor in an LTPO pixel circuit, and reduce the number of transistors, thereby to provide a narrow bezel.
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公开(公告)号：US20220328589A1
公开(公告)日：2022-10-13
申请号：US17437936
申请日：2020-10-27
发明人： Yipeng CHEN , Ling SHI , Wenqiang LI , Shuai XIE , Yang YU
IPC分类号： H01L27/32
摘要： This disclosure provides an array substrate and a display device. In the array substrate, the pixel driving circuit includes a driving transistor, a first transistor and a second transistor. The driving transistor and the first transistor are P-type transistors, and the second transistor is N-type transistor. The array substrate also includes a base substrate, and a first conductive layer arranged at a side of the base substrate and including: a first conductive portion forming a gate electrode of the driving transistor; a first gate line at a side of the first conductive portion, a part of the first gate line being configured to form a gate electrode of the first transistor; and a second gate line at a side of the first gate line away from the first conductive portion, a part of the second gate line being configured to form a first gate electrode of the second transistor.
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公开(公告)号：US20240040880A1
公开(公告)日：2024-02-01
申请号：US18483533
申请日：2023-10-10
发明人： Ling SHI , Ke LIU , Yipeng CHEN , Zhenhua ZHANG
IPC分类号： H10K59/35 , H10K59/131 , H10K59/179 , G09G3/3216 , G09G3/3225
CPC分类号： H10K59/353 , H10K59/131 , H10K59/179 , H10K59/351 , H10K59/352 , G09G3/3216 , G09G3/3225 , G09G2300/0426 , G09G2300/0452
摘要： A display panel includes a substrate, first light-emitting devices located in a first display area, a first driving circuit, second light-emitting devices located in a second display area, and a second driving circuit. The first driving circuit is configured to actively drive the first light-emitting devices to emit light, and includes a plurality of pixel driving circuits and a signal line. The signal line is located in the second display area, and extends along an edge of the second display area. An orthographic projection of the signal line on the substrate and an orthogonal projection of the first display area on the substrate have a gap therebetween. The second driving circuit is configured to passively drive the second light-emitting devices to emit light. An orthographic projection of at least one of the second light-emitting devices on the substrate is overlapped with an orthogonal projection of the gap on the substrate.
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公开(公告)号：US20230352110A1
公开(公告)日：2023-11-02
申请号：US18025633
申请日：2021-10-22
发明人： Zhu WANG , Ling SHI , Yipeng CHEN
摘要： Provided is a shift register. The shift register comprising: an input circuit, an intermediate circuit and an output circuit; the input circuit is connected to a first power supply terminal, a second power supply terminal, an input voltage terminal and a first clock signal terminal, and the input circuit is configured to output an intermediate input signal to the intermediate circuit; the intermediate circuit is connected to the first power supply terminal, the second power supply terminal and a second clock signal terminal, and the intermediate circuit is configured to output a first node signal to the output circuit; and the output circuit is connected to the first power supply terminal, the second power supply terminal, a first output terminal and a second output terminal, and the output circuit is configured to output a first output signal and a second output signal.
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公开(公告)号：US20220319420A1
公开(公告)日：2022-10-06
申请号：US17426562
申请日：2020-09-25
发明人： Yipeng CHEN , Ling SHI
IPC分类号： G09G3/3233
摘要： A pixel circuit, is provided, including: a light-emitting element, a driving circuit, a data writing circuit, an on-off control circuit, a first initialization circuit and an energy storage circuit; the data writing circuit writes a data voltage into a third node under control of a first gate driving signal; the on-off control circuit controls communication between a first node and the third node under the control of the first gate driving signal; the first initialization circuit controls writing an initialization voltage into the first node under the control of the first gate driving signal; and a type of a transistor included in the first initialization circuit is different from a type of a driving transistor included in the driving circuit, and a type of a transistor included in the data writing circuit is different from the type of the driving transistor of the driving circuit.
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公开(公告)号：US20240276814A1
公开(公告)日：2024-08-15
申请号：US18645441
申请日：2024-04-25
发明人： Benlian WANG , Li WANG , Yipeng CHEN , Yueping ZUO , Zheng LIU
IPC分类号： H10K59/131
CPC分类号： H10K59/131
摘要： A display panel and a display device are provided. The display panel comprises a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of wiring structures and a plurality of pads. The substrate comprises a display area and a non-display area comprising a bending area. The sub-pixels and data lines are in the display area and electrically connected with each other. The wiring structures are in the bending area and electrically connected with the data lines. At least one wiring structure comprises a plurality of hollow patterns connected successively, each hollow pattern comprises a first conductive part and a second conductive part connected with each other. The plurality of pads are in the non-display area and located on a side of the plurality of wiring structures away from the display area and electrically connected with the plurality of wiring structures.
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