SYSTEM AND METHOD FOR IDENTIFYING AND CLASSIFYING RESISTANCE GENES OF PLANT USING HIDDEN MARCOV MODEL
    1.
    发明申请
    SYSTEM AND METHOD FOR IDENTIFYING AND CLASSIFYING RESISTANCE GENES OF PLANT USING HIDDEN MARCOV MODEL 审中-公开
    使用隐藏MARCOV模型识别植物和分类抗性基因的系统和方法

    公开(公告)号:US20120271558A1

    公开(公告)日:2012-10-25

    申请号:US13515006

    申请日:2010-01-19

    IPC分类号: G06F19/24

    CPC分类号: G16B40/00

    摘要: The present invention relates to a system and a method for quickly and accurately identifying and classifying resistance genes of a plant from a protein or DNA sequence. In order to identify and classify resistance genes of a plant using a hidden marcov model, conceived is a profile matrix made using a protein sequence of a domain which is encoded by the resistance genes, and a system for identifying the domain of the resistance genes using the profile matrix and classifying the resistance genes by domain combination. The present invention enables effective identification and classification of the resistance genes of a plant using the profile matrix and program, of which the nucleotide base sequence or protein sequence is detected.

    摘要翻译: 本发明涉及从蛋白质或DNA序列快速准确地鉴定和分类植物的抗性基因的系统和方法。 为了使用隐藏的marcov模型来鉴定和分类植物的抗性基因,构想是使用由抗性基因编码的结构域的蛋白质序列制成的轮廓矩阵,以及用于鉴定抗性基因的结构域的系统,其使用 轮廓矩阵,并通过域组合对抗性基因进行分类。 本发明可以使用检测到核苷酸碱基序列或蛋白质序列的轮廓矩阵和程序有效地鉴定和分类植物的抗性基因。

    Integrated circuit card with a high voltage generator that selectively supplys high voltage to a first and second set of bitlines associated with a first and second memory block in paralell
    4.
    发明授权
    Integrated circuit card with a high voltage generator that selectively supplys high voltage to a first and second set of bitlines associated with a first and second memory block in paralell 有权
    具有高电压发生器的集成电路卡,其选择性地将高电压提供给与第一和第二组位线相关联的第一和第二存储器块

    公开(公告)号:US08631252B2

    公开(公告)日:2014-01-14

    申请号:US12717252

    申请日:2010-03-04

    申请人: Seung Won Lee

    发明人: Seung Won Lee

    IPC分类号: G06F1/00 G11C16/06

    摘要: Disclosed is an integrated circuit card which includes a central processing unit (CPU); a first memory block and a second memory block configured to operate responsive to a control of the CPU; and a high voltage generator block configured to generate a high voltage to be supplied to the first and second memory blocks. When bit lines of the first memory block are set by the high voltage, the CPU controls the high voltage generator block to supply the second memory block with the high voltage for a program operation of the second memory block during the program operation of the first memory block.

    摘要翻译: 公开了一种集成电路卡,其包括中央处理单元(CPU); 第一存储器块和第二存储器块,被配置为响应于CPU的控制而操作; 以及高电压发生器模块,被配置为产生要提供给所述第一和第二存储器块的高电压。 当第一存储器块的位线被高电压设置时,CPU在第一存储器的编程操作期间控制高电压发生器块以提供具有高电压的第二存储器块用于第二存储器块的编程操作 块。

    APPARATUS AND METHOD OF MANAGING DATABASES OF ACTIVE NODE AND STANDBY NODE OF MAIN MEMORY DATABASE MANAGEMENT SYSTEM
    5.
    发明申请
    APPARATUS AND METHOD OF MANAGING DATABASES OF ACTIVE NODE AND STANDBY NODE OF MAIN MEMORY DATABASE MANAGEMENT SYSTEM 有权
    主要内存数据库管理系统主动节点数据库和数据库管理数据库的设备与方法

    公开(公告)号:US20130151895A1

    公开(公告)日:2013-06-13

    申请号:US13456827

    申请日:2012-04-26

    申请人: Seung Won Lee

    发明人: Seung Won Lee

    IPC分类号: G06F11/14

    摘要: Databases of an active node and a standby node of a main memory database management system (MMDBMS) are managed so as to prevent loss of a transaction caused by failure of any one of the active node or the standby node. The MMDBMS is configured to prevent data mismatch between the active node and the standby node when failure of any one of the active node and the standby node occurs. In case of failure of one of the nodes, log information from the other node is obtained to recover the failed node.

    摘要翻译: 管理主存储器数据库管理系统(MMDBMS)的主动节点和备用节点的数据库,以防止任何一个主动节点或备​​用节点的故障导致的事务丢失。 MMDBMS被配置为在发生任何一个活动节点和备用节点的故障时防止活动节点和备用节点之间的数据不匹配。 在其中一个节点发生故障的情况下,获取另一个节点的日志信息来恢复故障节点。

    APPARTUS AND METHOD FOR THREAD PROGRESS TRACKING
    6.
    发明申请
    APPARTUS AND METHOD FOR THREAD PROGRESS TRACKING 有权
    用于进行进度跟踪的方法和方法

    公开(公告)号:US20130097613A1

    公开(公告)日:2013-04-18

    申请号:US13588228

    申请日:2012-08-17

    IPC分类号: G06F9/46

    摘要: Provided is a method and apparatus for measuring a progress or a performance of an application program in a computing environment using a micro-architecture. An apparatus for thread progress tracking may select a thread included in an application program, may determine, based on a predetermined criterion, whether an execution scheme for at least one instruction included in the thread corresponds to an effective execution scheme in which an execution time is uniform or a non-effective execution scheme in which a delayed cycle is included and the execution time is non-uniform, and may generate an effective progress index (EPI) by accumulating an execution time of an instruction executed by the effective execution scheme other than an instruction executed by the non-effective execution scheme.

    摘要翻译: 提供了一种用于在使用微架构的计算环境中测量应用程序的进度或性能的方法和装置。 用于线程进度跟踪的装置可以选择包括在应用程序中的线程,可以基于预定标准来确定包括在线程中的至少一条指令的执行方案是否对应于执行时间为 统一或非有效的执行方案,其中包括延迟循环并且执行时间不均匀,并且可以通过累积由除了有效执行方案之外的有效执行方案执行的指令的执行时间来生成有效进度索引(EPI) 由非有效执行方案执行的指令。

    METHOD OF DETERMINING MULTIMEDIA ARCHITECTURAL PATTERN, AND APPARATUS AND METHOD FOR TRANSFORMING SINGLE-CORE BASED ARCHITECTURE TO MULTI-CORE BASED ARCHITECTURE
    7.
    发明申请
    METHOD OF DETERMINING MULTIMEDIA ARCHITECTURAL PATTERN, AND APPARATUS AND METHOD FOR TRANSFORMING SINGLE-CORE BASED ARCHITECTURE TO MULTI-CORE BASED ARCHITECTURE 有权
    确定多媒体架构图案的方法,以及将基于单核架构的架构转换为多核架构的设备和方法

    公开(公告)号:US20120159428A1

    公开(公告)日:2012-06-21

    申请号:US13332008

    申请日:2011-12-20

    IPC分类号: G06F9/44

    CPC分类号: G06F8/314 G06F8/36

    摘要: A method and apparatus for authoring an architecture for transforming a single-core based embedded software application to a multi-core based embedded software application, and a method of determining an architectural pattern in a multimedia system. It is possible to perform an architecture authoring operation by using an architectural decision supporter, without prior knowledge and accumulated knowledge regarding a software architecture. Additionally, it is possible to prevent an error from occurring during authoring of an architecture, by using a concurrency-related software architectural pattern that is already evaluated. Thus, it is possible to improve overall quality of software, and to reduce a development time.

    摘要翻译: 一种用于创建用于将基于单核的嵌入式软件应用程序转换为基于多核的嵌入式软件应用程序的架构的方法和装置,以及确定多媒体系统中的架构模式的方法。 可以通过使用架构决策支持者来执行架构创作操作,而不需要有关软件架构的事先知识和积累的知识。 此外,可以通过使用已经评估的并发相关的软件体系结构模式来防止在创建架构期间发生错误。 因此,可以提高软件的整体质量,并且缩短开发时间。

    MOBILE TERMINAL AND METHOD FOR CONTROLLING THE MOBILE TERMINAL TO BE USED THROUGH HOST
    10.
    发明申请
    MOBILE TERMINAL AND METHOD FOR CONTROLLING THE MOBILE TERMINAL TO BE USED THROUGH HOST 审中-公开
    用于控制通过主机使用的移动终端的移动终端和方法

    公开(公告)号:US20100312919A1

    公开(公告)日:2010-12-09

    申请号:US12636443

    申请日:2009-12-11

    CPC分类号: G06F9/54

    摘要: A mobile terminal and a method for controlling the mobile terminal to be used through a host device are disclosed. The method for controlling the mobile terminal to be used through the host device includes transmitting a virtualization engine and driver programs of user modes of the mobile terminal to the host device; selecting one of the user modes; and transmitting information of the selected one user mode to the host device, wherein the transmitted virtualization engine is recognized as a part of an operating system (OS) of the host device, and is programmed to drive a driver program corresponding to each of the user modes within the host device.

    摘要翻译: 公开了一种用于通过主机设备来控制移动终端的移动终端和方法。 用于控制通过主机设备使用的移动终端的方法包括将虚拟化引擎和移动终端的用户模式的驱动程序传送到主机设备; 选择一种用户模式; 以及将所选择的一个用户模式的信息发送到所述主机设备,其中所述发送的虚拟化引擎被识别为所述主机设备的操作系统(OS)的一部分,并且被编程为驱动与所述用户中的每一个相对应的驱动程序 主机设备内的模式。