公开(公告)号：US07078332B2

公开(公告)日：2006-07-18

申请号：US10880035

申请日：2004-06-29

申请人： Cheol Mo Jeong ,  Tae Kyung Kim

发明人： Cheol Mo Jeong ,  Tae Kyung Kim

IPC分类号： H01L21/4763

CPC分类号： H01L27/105 ,  H01L21/76838 ,  H01L27/1052

摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising the steps of: providing a semiconductor substrate on which cell strings are formed and in which a plurality of conductive regions are formed; sequentially forming a first interlayer insulation film and a first etch barrier film on the semiconductor substrate; forming a plurality of contact holes by exposing the plurality of conductive regions formed in the semiconductor substrate, wherein an impurity concentration of the conductive regions is reduced due to the process for forming the contact holes; filling a metal material in the contact holes and forming a plurality of contact plugs; sequentially forming a second interlayer insulation film, a second etch barrier film and a third interlayer insulation film over a resulting structure including the contact plugs; forming a plurality of metal line patterns, wherein the metal line patterns pass through the third interlayer insulation film, the second etch barrier film and the second interlayer insulation film and contact to the contact plugs; forming a fourth interlayer insulation film over a resulting structure including the plurality of metal line patterns; forming a plurality of metal line contact holes by patterning the fourth interlayer insulation film; and forming a plurality of metal line contact plugs in the plurality of metal line contact holes by filling a metal material in the metal line contact holes.

摘要翻译： 本发明公开了一种制造半导体器件的方法，包括以下步骤：提供其上形成有多个导电区域的半导体衬底，其上形成有多个导电区域; 在半导体衬底上依次形成第一层间绝缘膜和第一蚀刻阻挡膜; 通过暴露形成在半导体衬底中的多个导电区域来形成多个接触孔，其中由于形成接触孔的工艺导致导电区域的杂质浓度降低; 在接触孔中填充金属材料并形成多个接触插塞; 在包括接触塞的所得结构上依次形成第二层间绝缘膜，第二蚀刻阻挡膜和第三层间绝缘膜; 形成多个金属线图案，其中所述金属线图案通过所述第三层间绝缘膜，所述第二蚀刻阻挡膜和所述第二层间绝缘膜并与所述接触插塞接触; 在包括所述多个金属线图案的所得结构上形成第四层间绝缘膜; 通过图案化第四层间绝缘膜形成多个金属线接触孔; 以及通过在金属线接触孔中填充金属材料在所述多个金属线接触孔中形成多个金属线接触塞。

公开(公告)号：US08138077B2

公开(公告)日：2012-03-20

申请号：US12464947

申请日：2009-05-13

申请人： Whee Won Cho ,  Nam Woo So ,  Cheol Mo Jeong ,  Eun Gyeong Jang, legal representative ,  Jung Geun Kim

发明人： Whee Won Cho ,  Nam Woo So ,  Cheol Mo Jeong ,  Jung Geun Kim

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

摘要： A flash memory device includes an isolation layer formed on an isolation region of a semiconductor substrate, a tunnel insulating layer formed on an active region of the semiconductor substrate, a first conductive layer formed over the tunnel insulating layer, a dielectric layer formed on the first conductive layer and the isolation layer, a first trench penetrating the dielectric layer on the isolation layer to separate parts of the dielectric layer, a second trench formed on the isolation layer and expanded from the first trench, and a second conductive layer formed over the dielectric layer to fill the first and second trenches.

摘要翻译： 闪速存储器件包括形成在半导体衬底的隔离区上的隔离层，形成在半导体衬底的有源区上的隧道绝缘层，形成在隧道绝缘层上的第一导电层，形成在第一 导电层和隔离层，穿过隔离层上的电介质层以分离电介质层的部分的第一沟槽，形成在隔离层上并从第一沟槽扩展的第二沟槽以及形成在电介质上的第二导电层 层以填充第一和第二沟槽。

公开(公告)号：US07521319B2

公开(公告)日：2009-04-21

申请号：US11646777

申请日：2006-12-28

申请人： Cheol Mo Jeong ,  Whee Won Cho ,  Jung Geun Kim ,  Seong Hwan Myung

发明人： Cheol Mo Jeong ,  Whee Won Cho ,  Jung Geun Kim ,  Seong Hwan Myung

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method of forming a gate of a flash memory device, including the steps of forming a gate on a semiconductor substrate and forming an oxide layer on the entire surface of the gate, forming a nitride layer on a sidewall of the oxide layer in a spacer form, performing a polishing process so that a top surface of the gate is exposed, and then stripping the nitride layer to form an opening, forming a barrier metal layer on a sidewall of the opening, and forming a tungsten layer in the opening.

摘要翻译： 一种形成闪速存储器件的栅极的方法，包括以下步骤：在半导体衬底上形成栅极并在栅极的整个表面上形成氧化物层，在间隔物的氧化物层的侧壁上形成氮化物层 形成，进行抛光处理使得栅极的顶表面露出，然后剥离氮化物层以形成开口，在开口的侧壁上形成阻挡金属层，并在开口中形成钨层。

公开(公告)号：US07390714B2

公开(公告)日：2008-06-24

申请号：US11164804

申请日：2005-12-06

申请人： Cheol Mo Jeong ,  Whee Won Cho ,  Jung Geun Kim

发明人： Cheol Mo Jeong ,  Whee Won Cho ,  Jung Geun Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/11521

摘要： Disclosed herein is a method of manufacturing semiconductor devices. The method includes the steps of forming a gate oxide film, a polysilicon film and a nitride film on a semiconductor substrate, and patterning the gate oxide film, the polysilicon film and the nitride film to form poly gates, forming a spacer at the side of the poly gate, forming a sacrifice nitride film on the entire surface, and then forming an interlayer insulation film on the entire surface, polishing the sacrifice nitride film formed on the interlayer insulation film and the poly gates so that the nitride film is exposed, removing top portions of the sacrifice nitride film while removing the nitride film, forming an insulation film spacer at the side exposed through removal of the nitride film, and filling a portion from which the sacrifice oxide film is removed with an insulation film, and forming the tungsten gates in portions from which the nitride films are moved.

摘要翻译： 这里公开了半导体器件的制造方法。 该方法包括在半导体衬底上形成栅极氧化膜，多晶硅膜和氮化物膜的步骤，以及对栅极氧化膜，多晶硅膜和氮化物膜进行构图以形成多晶硅栅极，在 在整个表面上形成牺牲氮化物膜，然后在整个表面上形成层间绝缘膜，研磨在层间绝缘膜和多晶硅栅上形成的牺牲氮化物膜，使得氮化物膜露出，去除 牺牲氮化物膜的顶部，同时去除氮化物膜，在通过去除氮化物膜暴露的一侧形成绝缘膜间隔物，并且用绝缘膜填充去除牺牲氧化物膜的部分，并形成钨 栅极在其中移动氮化物膜的部分中。

公开(公告)号：US20080102579A1

公开(公告)日：2008-05-01

申请号：US11617690

申请日：2006-12-28

申请人： Cha Deok Dong ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

发明人： Cha Deok Dong ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

IPC分类号： H01L21/8242

CPC分类号： H01L27/11521 ,  H01L21/76232

摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.

摘要翻译： 形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。 间隔件形成在每个第一沟槽的侧壁上。 第二沟槽形成在对应的第一沟槽下方的隔离区域中。 每个第二沟槽比相应的第一沟槽更窄和更深。 第一氧化物层形成在每个第二沟槽的侧壁和底表面上。 第一沟槽填充有绝缘层。

公开(公告)号：US20080003823A1

公开(公告)日：2008-01-03

申请号：US11647765

申请日：2006-12-29

申请人： Whee Won Cho ,  Seung Hee Hong ,  Suk Joong Kim ,  Cheol Mo Jeong

发明人： Whee Won Cho ,  Seung Hee Hong ,  Suk Joong Kim ,  Cheol Mo Jeong

IPC分类号： H01L21/44 ,  H01L21/465

CPC分类号： H01L21/76829 ,  H01L21/76802 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device includes the steps of forming an interlayer insulating layer and an etch-stop nitride layer over a semiconductor substrate, etching the etch-stop nitride layer and the interlayer insulating layer to form contact holes, forming contacts in the contact holes, forming an oxide layer on the entire surface including the contacts, etching the oxide layer using the etch-stop nitride layer as a target, thus forming trenches through which the contacts and the etch-stop nitride layer adjacent to the contacts are exposed, and forming bit lines in the trenches.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成层间绝缘层和蚀刻停止氮化物层，蚀刻蚀刻停止氮化物层和层间绝缘层以形成接触孔，在触点中形成触点 在包括触点的整个表面上形成氧化物层，使用蚀刻 - 停留氮化物层作为靶蚀刻氧化层，从而形成沟槽，触点和与触点相邻的蚀刻 - 停止氮化物层通过该沟槽暴露， 并在沟槽中形成位线。

公开(公告)号：US07629213B2

公开(公告)日：2009-12-08

申请号：US11647628

申请日：2006-12-29

申请人： Whee Won Cho ,  Jung Geun Kim ,  Seong Hwan Myung ,  Cheol Mo Jeong

发明人： Whee Won Cho ,  Jung Geun Kim ,  Seong Hwan Myung ,  Cheol Mo Jeong

IPC分类号： H01L21/8238

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521

摘要： A method of manufacturing a flash memory device includes the steps of forming gate patterns for cells and gate patterns for select transistors over a semiconductor substrate, forming a buffer insulating layer on the resulting surface including the gate patterns, forming an insulating layer to form void in spaces between the gate patterns for cells, forming a nitride layer on the insulating layer, and forming a spacer on one side of each of the gate patterns for select transistors by a spacer etch process.

摘要翻译： 一种制造闪速存储器件的方法包括以下步骤：在半导体衬底上形成用于单元的栅极图案和用于选择晶体管的栅极图案，在包含栅极图案的所得表面上形成缓冲绝缘层，形成绝缘层以形成空隙 用于单元的栅极图案之间的间隔，在绝缘层上形成氮化物层，并且通过间隔物蚀刻工艺在用于选择晶体管的每个栅极图案的一侧上形成间隔物。

公开(公告)号：US20090283818A1

公开(公告)日：2009-11-19

申请号：US12464947

申请日：2009-05-13

申请人： Whee Won Cho ,  Nam Woo So ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Eun Gyeong Jang

发明人： Whee Won Cho ,  Nam Woo So ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Eun Gyeong Jang

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

摘要： A flash memory device includes an isolation layer formed on an isolation region of a semiconductor substrate, a tunnel insulating layer formed on an active region of the semiconductor substrate, a first conductive layer formed over the tunnel insulating layer, a dielectric layer formed on the first conductive layer and the isolation layer, the dielectric layer having a groove for exposing the isolation layer, a trench formed on the isolation layer and exposed through the groove, and a second conductive layer formed over the dielectric layer the trench.

摘要翻译： 闪速存储器件包括形成在半导体衬底的隔离区上的隔离层，形成在半导体衬底的有源区上的隧道绝缘层，形成在隧道绝缘层上的第一导电层，形成在第一 所述绝缘层具有用于暴露所述隔离层的沟槽，形成在所述隔离层上并通过所述沟槽露出的沟槽以及在所述电介质层上形成所述沟槽的第二导电层。

公开(公告)号：US20090098740A1

公开(公告)日：2009-04-16

申请号：US12163328

申请日：2008-06-27

申请人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho

发明人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76232

摘要： The invention discloses a method of forming an isolation layer in a semiconductor device. The method includes providing a semiconductor substrate having a trench formed therein; forming a first insulating layer in the trench; and forming a densified second insulating layer on the first insulating layer. In the above method, a void is not generated in the isolation layer so a bending phenomenon of an active region can be reduced or prevented to improve an electrical characteristic of the semiconductor.

摘要翻译： 本发明公开了一种在半导体器件中形成隔离层的方法。 该方法包括提供其中形成有沟槽的半导体衬底; 在沟槽中形成第一绝缘层; 以及在所述第一绝缘层上形成致密的第二绝缘层。 在上述方法中，在隔离层中不会产生空隙，因此可以减少或防止有源区的弯曲现象来改善半导体的电特性。

公开(公告)号：US07462536B2

公开(公告)日：2008-12-09

申请号：US11680500

申请日：2007-02-28

申请人： Cheol Mo Jeong ,  Whee Won Cho ,  Jung Geun Kim ,  Seung Hee Hong

发明人： Cheol Mo Jeong ,  Whee Won Cho ,  Jung Geun Kim ,  Seung Hee Hong

IPC分类号： H01L21/336

CPC分类号： H01L21/7684 ,  H01L27/10885

摘要： A method of forming a bit line of a semiconductor memory device is performed as follows. A first interlayer insulating layer is formed over a semiconductor substrate in which an underlying structure is formed. A region of the first interlayer insulating layer is etched to form contact holes through which a contact region of the semiconductor substrate is exposed. A low-resistance tungsten layer is deposited on the entire surface including the contact holes, thus forming contacts. A CMP process is performed in order to mitigate surface roughness of the low-resistance tungsten layer. The low-resistance tungsten layer on the interlayer insulating layer is patterned in a bit line metal line pattern, forming a bit line.

摘要翻译： 如下进行形成半​​导体存储器件的位线的方法。 第一层间绝缘层形成在形成下面的结构的半导体衬底上。 蚀刻第一层间绝缘层的区域以形成暴露半导体衬底的接触区域的接触孔。 在包括接触孔的整个表面上沉积低电阻钨层，从而形成接触。 执行CMP工艺以减轻低电阻钨层的表面粗糙度。 将层间绝缘层上的低电阻钨层图案化为位线金属线图案，形成位线。