公开(公告)号：US07547938B2

公开(公告)日：2009-06-16

申请号：US11954349

申请日：2007-12-12

申请人： Cheol-ju Yun ,  Tae-young Chung ,  Dong-jun Lee

发明人： Cheol-ju Yun ,  Tae-young Chung ,  Dong-jun Lee

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10888 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10891

摘要： A method of manufacturing a semiconductor device includes forming conductive structures on a substrate. Each of the conductive structures has a line shape that extends along a first direction parallel to the substrate. Insulating spacers are formed on upper sidewalls of the conductive structures. An insulating interlayer is formed that covers the conductive structures. A portion of the insulating interlayer between the conductive structures is etched to form a contact hole. An upper portion of the contact hole is larger than a lower portion thereof. The upper portion of the contact hole has a first width along the first direction and a second width along a second direction parallel to the substrate and substantially perpendicular to the first direction. The first width is substantially larger than the second width. The contact hole is filled with a conductive material to form a contact plug.

摘要翻译： 制造半导体器件的方法包括在衬底上形成导电结构。 每个导电结构具有沿平行于基板的第一方向延伸的线状。 绝缘垫片形成在导电结构的上侧壁上。 形成覆盖导电结构的绝缘中间层。 导电结构之间的绝缘中间层的一部分被蚀刻以形成接触孔。 接触孔的上部大于其下部。 接触孔的上部具有沿着第一方向的第一宽度和沿着平行于基底并基本上垂直于第一方向的第二方向的第二宽度。 第一宽度基本上大于第二宽度。 接触孔填充有导电材料以形成接触塞。

公开(公告)号：US20080088025A1

公开(公告)日：2008-04-17

申请号：US11954349

申请日：2007-12-12

申请人： Cheol-ju Yun ,  Tae-young Chung ,  Dong-jun Lee

发明人： Cheol-ju Yun ,  Tae-young Chung ,  Dong-jun Lee

IPC分类号： H01L23/48

CPC分类号： H01L27/10888 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10891

摘要： A method of manufacturing a semiconductor device includes forming conductive structures on a substrate. Each of the conductive structures has a line shape that extends along a first direction parallel to the substrate. Insulating spacers are formed on upper sidewalls of the conductive structures. An insulating interlayer is formed that covers the conductive structures. A portion of the insulating interlayer between the conductive structures is etched to form a contact hole. An upper portion of the contact hole is larger than a lower portion thereof. The upper portion of the contact hole has a first width along the first direction and a second width along a second direction parallel to the substrate and substantially perpendicular to the first direction. The first width is substantially larger than the second width. The contact hole is filled with a conductive material to form a contact plug.

摘要翻译： 制造半导体器件的方法包括在衬底上形成导电结构。 每个导电结构具有沿平行于基板的第一方向延伸的线状。 绝缘垫片形成在导电结构的上侧壁上。 形成覆盖导电结构的绝缘中间层。 导电结构之间的绝缘中间层的一部分被蚀刻以形成接触孔。 接触孔的上部大于其下部。 接触孔的上部具有沿着第一方向的第一宽度和沿着平行于基底并基本上垂直于第一方向的第二方向的第二宽度。 第一宽度基本上大于第二宽度。 接触孔填充有导电材料以形成接触塞。

公开(公告)号：US07326613B2

公开(公告)日：2008-02-05

申请号：US11096129

申请日：2005-03-31

申请人： Cheol-ju Yun ,  Tae-young Chung ,  Dong-jun Lee

发明人： Cheol-ju Yun ,  Tae-young Chung ,  Dong-jun Lee

IPC分类号： H01L21/8242

CPC分类号： H01L27/10888 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10891

摘要： A method of manufacturing a semiconductor device includes forming conductive structures on a substrate. Each of the conductive structures has a line shape that extends along a first direction parallel to the substrate. Insulating spacers are formed on upper sidewalls of the conductive structures. An insulating interlayer is formed that covers the conductive structures. A portion of the insulating interlayer between the conductive structures is etched to form a contact hole. An upper portion of the contact hole is larger than a lower portion thereof. The upper portion of the contact hole has a first width along the first direction and a second width along a second direction parallel to the substrate and substantially perpendicular to the first direction. The first width is substantially larger than the second width. The contact hole is filled with a conductive material to form a contact plug.

摘要翻译： 制造半导体器件的方法包括在衬底上形成导电结构。 每个导电结构具有沿平行于基板的第一方向延伸的线状。 绝缘垫片形成在导电结构的上侧壁上。 形成覆盖导电结构的绝缘中间层。 导电结构之间的绝缘中间层的一部分被蚀刻以形成接触孔。 接触孔的上部大于其下部。 接触孔的上部具有沿着第一方向的第一宽度和沿着平行于基底并基本上垂直于第一方向的第二方向的第二宽度。 第一宽度基本上大于第二宽度。 接触孔填充有导电材料以形成接触塞。

公开(公告)号：US20050218408A1

公开(公告)日：2005-10-06

申请号：US11096129

申请日：2005-03-31

申请人： Cheol-ju Yun ,  Tae-young Chung ,  Dong-jun Lee

发明人： Cheol-ju Yun ,  Tae-young Chung ,  Dong-jun Lee

IPC分类号： H01L27/108 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L29/12

CPC分类号： H01L27/10888 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10891

摘要： A method of manufacturing a semiconductor device includes forming conductive structures on a substrate. Each of the conductive structures has a line shape that extends along a first direction parallel to the substrate. Insulating spacers are formed on upper sidewalls of the conductive structures. An insulating interlayer is formed that covers the conductive structures. A portion of the insulating interlayer between the conductive structures is etched to form a contact hole. An upper portion of the contact hole is larger than a lower portion thereof. The upper portion of the contact hole has a first width along the first direction and a second width along a second direction parallel to the substrate and substantially perpendicular to the first direction. The first width is substantially larger than the second width. The contact hole is filled with a conductive material to form a contact plug.

摘要翻译： 制造半导体器件的方法包括在衬底上形成导电结构。 每个导电结构具有沿平行于基板的第一方向延伸的线状。 绝缘垫片形成在导电结构的上侧壁上。 形成覆盖导电结构的绝缘中间层。 导电结构之间的绝缘中间层的一部分被蚀刻以形成接触孔。 接触孔的上部大于其下部。 接触孔的上部具有沿着第一方向的第一宽度和沿着平行于基底并基本上垂直于第一方向的第二方向的第二宽度。 第一宽度基本上大于第二宽度。 接触孔填充有导电材料以形成接触塞。

公开(公告)号：US06635582B2

公开(公告)日：2003-10-21

申请号：US09270229

申请日：1999-03-15

申请人： Cheol-ju Yun ,  Young-min Kwon ,  Heung-soo Park

发明人： Cheol-ju Yun ,  Young-min Kwon ,  Heung-soo Park

IPC分类号： H01L21302

CPC分类号： H01L21/02071 ,  G03F7/422 ,  H01L21/76838

摘要： A pre-stripping treatment solution for treatment of metal surfaces before stripping photoresist which has been used for patterning a metal layer. Also provided is a method of removing the photoresist, and a method of manufacturing semiconductor devices using the above solution and method. In one aspect of the invention, the photoresist is first ashed. The ashed resultant structure is then treated, prior to stripping of the photoresist, with a pre-stripping treatment solution of an organic acid solution having a carboxyl group is mixed with deionized water at a volume ratio of 1:0 to 1:100.

摘要翻译： 用于在剥离已经用于图案化金属层的光致抗蚀剂之前处理金属表面的预剥离处理溶液。 还提供了去除光致抗蚀剂的方法，以及使用上述溶液和方法制造半导体器件的方法。 在本发明的一个方面，首先将光致抗蚀剂灰化。 然后在剥离光致抗蚀剂之前，将具有羧基的有机酸溶液的预剥离处理溶液以1：0至1：100的体积比与去离子水混合，然后处理灰化的所得结构。

公开(公告)号：US07030439B2

公开(公告)日：2006-04-18

申请号：US10704514

申请日：2003-11-07

申请人： Cheol-ju Yun ,  Sun-hoo Park

发明人： Cheol-ju Yun ,  Sun-hoo Park

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/0207 ,  H01L27/10808 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/91

摘要： A DRAM memory cell includes a semiconductor substrate, an interlayer dielectric having storage node contact plugs that is formed on the semiconductor substrate, and storage node electrodes that are formed on the interlayer dielectric to contact the storage node contact plugs. The storage node contact plugs are formed such that an entrance portion is formed to be larger in linewidth than a contacting portions, and they are formed in gaps between the bit line structures. From a plan view perspective, the storage node electrodes of one column are offset from the storage node contact plugs in an adjacent column, such that the storage node electrodes are in a diagonal arrangement throughout the semiconductor substrate.

摘要翻译： DRAM存储单元包括半导体衬底，形成在半导体衬底上的存储节点接触插塞的层间电介质和形成在层间电介质上以与存储节点接触插头接触的存储节点电极。 存储节点接触插塞形成为使得入口部分形成为比接触部分更大的线宽，并且它们形成在位线结构之间的间隙中。 从平面图的观点来看，一列的存储节点电极偏离相邻列中的存储节点接触插塞，使得存储节点电极在贯穿整个半导体衬底的对角排列。

公开(公告)号：US07321146B2

公开(公告)日：2008-01-22

申请号：US11352179

申请日：2006-02-10

申请人： Cheol-ju Yun ,  Sun-hoo Park

发明人： Cheol-ju Yun ,  Sun-hoo Park

IPC分类号： H01L27/108

CPC分类号： H01L27/0207 ,  H01L27/10808 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/91

摘要： A DRAM memory cell includes a semiconductor substrate, an interlayer dielectric having storage node contact plugs that is formed on the semiconductor substrate, and storage node electrodes that are formed on the interlayer dielectric to contact the storage node contact plugs. The storage node contact plugs are formed such that an entrance portion is formed to be larger in linewidth than a contacting portions, and they are formed in gaps between the bit line structures. From a plan view perspective, the storage node electrodes of one column are offset from the storage node contact plugs in an adjacent column, such that the storage node electrodes are in a diagonal arrangement throughout the semiconductor substrate.

摘要翻译： DRAM存储单元包括半导体衬底，形成在半导体衬底上的存储节点接触插塞的层间电介质和形成在层间电介质上以与存储节点接触插塞接触的存储节点电极。 存储节点接触插塞形成为使得入口部分形成为比接触部分更大的线宽，并且它们形成在位线结构之间的间隙中。 从平面图的观点来看，一列的存储节点电极偏离相邻列中的存储节点接触插塞，使得存储节点电极在贯穿整个半导体衬底的对角排列。

公开(公告)号：US07166507B2

公开(公告)日：2007-01-23

申请号：US10774081

申请日：2004-02-05

申请人： Cheol-ju Yun

发明人： Cheol-ju Yun

IPC分类号： H01L21/8242

CPC分类号： H01L27/10814 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to some embodiments of the invention, bit lines are formed using a multi-layered hard mask and BC nodes are separated by forming line-type BCs in the same direction of gate lines. Thus, a narrowing of shoulders between the bit lines and the BCs can be prevented, and spacers can be formed of a low k-dielectric silicon oxide, thereby lowering parasitic capacitance.

摘要翻译： 根据本发明的一些实施例，使用多层硬掩模形成位线，并且通过在栅极线的相同方向上形成线型BC来分离BC节点。 因此，可以防止位线和BC之间的肩部变窄，并且间隔物可以由低k电介质氧化硅形成，从而降低寄生电容。

公开(公告)号：US20060057783A1

公开(公告)日：2006-03-16

申请号：US11225789

申请日：2005-09-13

申请人： Cheol-ju Yun ,  Bo-sung Kim ,  Huck-jin Kang

发明人： Cheol-ju Yun ,  Bo-sung Kim ,  Huck-jin Kang

IPC分类号： H01L21/82

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a fuse in a semiconductor device can be provided by selectively removing an inter-metal insulator to expose a fuse capping layer by recessing the inter-metal insulator around the fuse and removing the capping layer from the fuse to expose a fuse metal film thereunder.

摘要翻译： 在半导体器件中形成熔丝的方法可以通过选择性地去除金属间绝缘体以通过使金属间绝缘体围绕保险丝凹陷并从保险丝去除覆盖层以暴露熔丝金属熔体来露出熔丝盖层来提供 电影片段。

公开(公告)号：US20060124979A1

公开(公告)日：2006-06-15

申请号：US11352179

申请日：2006-02-10

申请人： Cheol-ju Yun ,  Sun-hoo Park

发明人： Cheol-ju Yun ,  Sun-hoo Park

IPC分类号： H01L29/94

CPC分类号： H01L27/0207 ,  H01L27/10808 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/91

摘要： A DRAM memory cell includes a semiconductor substrate, an interlayer dielectric having storage node contact plugs that is formed on the semiconductor substrate, and storage node electrodes that are formed on the interlayer dielectric to contact the storage node contact plugs. The storage node contact plugs are formed such that an entrance portion is formed to be larger in linewidth than a contacting portions, and they are formed in gaps between the bit line structures. From a plan view perspective, the storage node electrodes of one column are offset from the storage node contact plugs in an adjacent column, such that the storage node electrodes are in a diagonal arrangement throughout the semiconductor substrate.

摘要翻译： DRAM存储单元包括半导体衬底，形成在半导体衬底上的存储节点接触插塞的层间电介质和形成在层间电介质上以与存储节点接触插头接触的存储节点电极。 存储节点接触插塞形成为使得入口部分形成为比接触部分更大的线宽，并且它们形成在位线结构之间的间隙中。 从平面图的观点来看，一列的存储节点电极偏离相邻列中的存储节点接触插塞，使得存储节点电极在贯穿整个半导体衬底的对角排列。