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公开(公告)号:US20140028543A1
公开(公告)日:2014-01-30
申请号:US13562168
申请日:2012-07-30
申请人: Chi Shun Lo , Je-Hsiung Jeffrey Lan , Mario Francisco Velez , Robert Paul Mikulka , Chengjie Zuo , Changhan Hobie Yun , Jonghae Kim
发明人: Chi Shun Lo , Je-Hsiung Jeffrey Lan , Mario Francisco Velez , Robert Paul Mikulka , Chengjie Zuo , Changhan Hobie Yun , Jonghae Kim
CPC分类号: H01F17/0006 , G02B26/001 , H01F27/2804 , H01L23/5227 , H01L28/10 , H01L2924/00 , H01L2924/0002
摘要: This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces.
摘要翻译: 本公开提供了诸如无源器件的集成电路结构中的通孔的系统,方法和装置。 一方面,集成无源器件包括在第一导电迹线上的第一导电迹线和第二导电迹线,在第一导电迹线的一部分和第二导电迹线之间具有层间电介质。 在层间电介质中提供一个或多个通孔以提供第一导电迹线和第二导电迹线之间的电连接。 通孔的宽度大于至少一个导电迹线的宽度。
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公开(公告)号:US09001031B2
公开(公告)日:2015-04-07
申请号:US13562168
申请日:2012-07-30
申请人: Chi Shun Lo , Je-Hsiung Jeffrey Lan , Mario Francisco Velez , Robert Paul Mikulka , Chengjie Zuo , Changhan Hobie Yun , Jonghae Kim
发明人: Chi Shun Lo , Je-Hsiung Jeffrey Lan , Mario Francisco Velez , Robert Paul Mikulka , Chengjie Zuo , Changhan Hobie Yun , Jonghae Kim
CPC分类号: H01F17/0006 , G02B26/001 , H01F27/2804 , H01L23/5227 , H01L28/10 , H01L2924/00 , H01L2924/0002
摘要: This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces.
摘要翻译: 本公开提供了诸如无源器件的集成电路结构中的通孔的系统,方法和装置。 一方面,集成无源器件包括在第一导电迹线上的第一导电迹线和第二导电迹线,在第一导电迹线的一部分和第二导电迹线之间具有层间电介质。 在层间电介质中提供一个或多个通孔以提供第一导电迹线和第二导电迹线之间的电连接。 通孔的宽度大于至少一个导电迹线的宽度。
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