公开(公告)号：US20080127356A1

公开(公告)日：2008-05-29

申请号：US11563233

申请日：2006-11-27

申请人： Chi-Chun Hsu ,  Yuh-Long Yeh ,  Ming-Yang Chao

发明人： Chi-Chun Hsu ,  Yuh-Long Yeh ,  Ming-Yang Chao

IPC分类号： G06F12/14

CPC分类号： G06F21/78 ,  G06F21/572 ,  G06F21/575 ,  G06F21/62 ,  G06F21/6209

摘要： A method for securing firmware in a memory is provided. Memory data in the memory is checked. If the memory data in the memory meets a criterion, a host is allowed to read and write the entire memory. If not, the host is prevented from reading the entire memory.

摘要翻译： 提供了一种用于将固件固定在存储器中的方法。 检查内存中的内存数据。 如果存储器中的存储器数据满足标准，则允许主机读取和写入整个存储器。 如果不是，主机被阻止读取整个内存。

公开(公告)号：US20090013192A1

公开(公告)日：2009-01-08

申请号：US11772829

申请日：2007-07-03

申请人： Ping-Sheng Chen ,  Ming-Yang Chao ,  Chi-Chun Hsu ,  Yao-Dun Chang ,  Tse-Hong Wu

发明人： Ping-Sheng Chen ,  Ming-Yang Chao ,  Chi-Chun Hsu ,  Yao-Dun Chang ,  Tse-Hong Wu

IPC分类号： G06F12/14

CPC分类号： G06F11/1004

摘要： An integrity check method applied to an electronic device includes: fetching at least one portion of external data into a specific memory, where the external data is stored within the electronic device; during fetching the portion of the external data into the specific memory, checking whether the size of the fetched data in the specific memory reaches a predetermined value, where the predetermined value is less than the total size of the external data; and when the size of the fetched data in the specific memory reaches the predetermined value, enabling an integrity check of the fetched data.

摘要翻译： 应用于电子设备的完整性检查方法包括：将外部数据的至少一部分取出到特定存储器中，其中外部数据存储在电子设备内; 在将外部数据的一部分取入特定存储器期间，检查特定存储器中的获取的数据的大小是否达到预定值，其中预定值小于外部数据的总大小; 并且当特定存储器中的获取的数据的大小达到预定值时，能够对获取的数据进行完整性检查。

公开(公告)号：US07049874B2

公开(公告)日：2006-05-23

申请号：US10695747

申请日：2003-10-30

申请人： Chih-Ching Chen ,  Jyh-Shin Pan ,  Ming-Yang Chao ,  Yi Kwang Hu

发明人： Chih-Ching Chen ,  Jyh-Shin Pan ,  Ming-Yang Chao ,  Yi Kwang Hu

IPC分类号： H03H11/26

CPC分类号： H04M3/02 ,  H04M2201/14

摘要： A digital delaying device for delaying an input signal includes a ring oscillator, a calibration unit, and at least one delay number calculation unit and delay channel. The ring oscillator includes loop-connected delay cells for outputting an oscillation clock. The calibration unit receives a reference clock and the oscillation clock and calculates a pulse number of the oscillation clock corresponding to each reference clock period. The pulse number serves as a period reference pulse number. The calculation unit receives the pulse number and a signal delay value, calculates a signal delay number corresponding to the signal delay value according to the pulse number, and outputs a selection signal. The delay channel includes a multiplexer and cascaded delay cells, which receives an input signal and generates delay signals with different delay timings. The multiplexer selects and outputs one of the delay signals as an output signal according to the selection signal.

摘要翻译： 用于延迟输入信号的数字延迟装置包括环形振荡器，校准单元和至少一个延迟数计算单元和延迟信道。 环形振荡器包括用于输出振荡时钟的环路连接的延迟单元。 校准单元接收参考时钟和振荡时钟，并计算对应于每个参考时钟周期的振荡时钟的脉冲数。 脉冲数用作周期参考脉冲数。 计算单元接收脉冲数和信号延迟值，根据脉冲数计算与信号延迟值对应的信号延迟数，并输出选择信号。 延迟通道包括多路复用器和级联延迟单元，其接收输入信号并产生具有不同延迟定时的延迟信号。 多路复用器根据选择信号选择并输出一个延迟信号作为输出信号。

公开(公告)号：US20050172036A1

公开(公告)日：2005-08-04

申请号：US10709551

申请日：2004-05-13

申请人： Yao-Jen Liang ,  Ming-Yang Chao

发明人： Yao-Jen Liang ,  Ming-Yang Chao

IPC分类号： G06F3/00 ,  G06F13/42

CPC分类号： G06F13/4208

摘要： A multi-chip system has at least a host chip and at least a slave chip. The slave chip informs the host chip of data needed to be transmitted. When informed by the slave chip the host chip informs the slave chip to start to transmit the data, and when informed by the host chip the slave chip starts to transmit the data to the host chip.

摘要翻译： 多芯片系统至少具有主芯片和至少一个从芯片。 从芯片向主机芯片通知需要发送的数据。 当从机芯片通知主机芯片通知从机芯片开始发送数据时，当主机芯片通知从机芯片开始向主机芯片发送数据时，

公开(公告)号：US08112439B2

公开(公告)日：2012-02-07

申请号：US12236823

申请日：2008-09-24

申请人： Ching-Wen Hsueh ,  Ming-Yang Chao

发明人： Ching-Wen Hsueh ,  Ming-Yang Chao

IPC分类号： G06F7/00 ,  G06F17/30

CPC分类号： H04L27/2614

摘要： A data processing system is disclosed. The system includes a processor, a transformer, a first memory buffer, a second memory buffer, a first filter, and a second filter. An obtained transmission signal symbol is first transformed to first data. The first memory buffer stores the first data. The processor obtains peak data based on the first data according to a predetermined threshold. The transformer transforms the peak data to second data and stores the second data in the second memory buffer. The first filter filters the second data to determine reserved data of the second data and removes the reserved data from the second data to generate third data. The transformer transforms the third data to fourth data and stores the fourth data in the second memory buffer. The processor merges the first and fourth data to generate fifth data. The second filter filters the fifth data based on the transmission signal symbol and a previously obtained transmission signal symbol.

摘要翻译： 公开了一种数据处理系统。 该系统包括处理器，变压器，第一存储器缓冲器，第二存储器缓冲器，第一过滤器和第二过滤器。 获得的发送信号符号首先被变换为第一数据。 第一存储器缓冲器存储第一数据。 处理器根据预定阈值基于第一数据获得峰值数据。 变压器将峰值数据变换为第二数据，并将第二数据存储在第二存储器缓冲器中。 第一滤波器对第二数据进行滤波以确定第二数据的保留数据，并从第二数据中移除预留数据以产生第三数据。 变压器将第三数据变换为第四数据，并将第四数据存储在第二存储器缓冲器中。 处理器合并第一和第四数据以产生第五数据。 第二滤波器基于发送信号符号和先前获得的发送信号符号对第五数据进行滤波。

公开(公告)号：US20080155377A1

公开(公告)日：2008-06-26

申请号：US11643296

申请日：2006-12-21

申请人： Ming-Yang Chao ,  Ching-Wen Hsueh

发明人： Ming-Yang Chao ,  Ching-Wen Hsueh

IPC分类号： H03M13/17 ,  G11C29/00 ,  G06F11/07

CPC分类号： G11B20/1833 ,  G11B19/041 ,  G11B2220/2541 ,  H03M13/27 ,  H03M13/2954

摘要： An optical storage medium recording apparatus is provided a data preparing and ECC encoding circuit that both prepares the data by combining different categories of data into data sequences in accordance with a data layout on the optical storage medium and encodes the combined data. The encoded data is temporarily stored in a data buffer, and subsequently successively read out by a recording circuit for recording onto the optical storage medium according to the data layout. For a Blu-ray disc recording apparatus, the data preparing and ECC encoding circuit includes a LDC/BIS encoder for generating long distance error correction codes (LDC) and burst indicator subcodes (BIS) from the combined data to form LDC and BIS encoded data, which is temporarily stored in the data buffer. The recording circuit includes an interleave circuit for interleaving the LDC and BIS data to form physical clusters for recording on the disc.

摘要翻译： 光存储介质记录装置提供有数据准备和ECC编码电路，它们通过根据光学存储介质上的数据布局将不同类别的数据组合成数据序列来准备数据，并对组合的数据进行编码。 编码数据被临时存储在数据缓冲器中，并且随后根据数据布局由用于记录到光存储介质上的记录电路连续地读出。 对于蓝光盘记录装置，数据准备和ECC编码电路包括用于从组合数据生成长距离纠错码（LDC）和突发指示符子码（BIS）的LDC / BIS编码器，以形成LDC和BIS编码数据 ，它暂时存储在数据缓冲区中。 记录电路包括用于交织LDC和BIS数据以形成用于在盘上记录的物理簇的交织电路。

公开(公告)号：US07975208B2

公开(公告)日：2011-07-05

申请号：US11643296

申请日：2006-12-21

申请人： Ming-Yang Chao ,  Ching-Wen Hsueh

发明人： Ming-Yang Chao ,  Ching-Wen Hsueh

IPC分类号： G11B20/18

CPC分类号： G11B20/1833 ,  G11B19/041 ,  G11B2220/2541 ,  H03M13/27 ,  H03M13/2954

摘要： An optical storage medium recording apparatus is provided a data preparing and ECC encoding circuit that both prepares the data by combining different categories of data into data sequences in accordance with a data layout on the optical storage medium and encodes the combined data. The encoded data is temporarily stored in a data buffer, and subsequently successively read out by a recording circuit for recording onto the optical storage medium according to the data layout. For a Blu-ray disc recording apparatus, the data preparing and ECC encoding circuit includes a LDC/BIS encoder for generating long distance error correction codes (LDC) and burst indicator subcodes (BIS) from the combined data to form LDC and BIS encoded data, which is temporarily stored in the data buffer. The recording circuit includes an interleave circuit for interleaving the LDC and BIS data to form physical clusters for recording on the disc.

摘要翻译： 光存储介质记录装置提供有数据准备和ECC编码电路，它们通过根据光学存储介质上的数据布局将不同类别的数据组合成数据序列来准备数据，并对组合的数据进行编码。 编码数据被临时存储在数据缓冲器中，并且随后根据数据布局由用于记录到光存储介质上的记录电路连续地读出。 对于蓝光盘记录装置，数据准备和ECC编码电路包括用于从组合数据生成长距离纠错码（LDC）和突发指示符子码（BIS）的LDC / BIS编码器，以形成LDC和BIS编码数据 ，它暂时存储在数据缓冲区中。 记录电路包括用于交织LDC和BIS数据以形成用于在盘上记录的物理簇的交织电路。

公开(公告)号：US20090024784A1

公开(公告)日：2009-01-22

申请号：US11780490

申请日：2007-07-20

申请人： Liang-Yun Wang ,  Yao-Dun Chang ,  Ming-Yang Chao ,  Ping-Sheng Chen

发明人： Liang-Yun Wang ,  Yao-Dun Chang ,  Ming-Yang Chao ,  Ping-Sheng Chen

IPC分类号： G06F12/00

CPC分类号： G06F21/572

摘要： Disclosed are a method for writing data into a first storage on a chip and a system thereof. The method includes storing an initial firmware into a second storage on the chip, programming the first storage according to a specific data by utilizing the initial firmware, and blocking further programming operations applied to at least part of the specific data after the specific data is successfully stored in the first storage. Therefore the invention can save the external pin connections of the chip to prevent computer hackers from accessing or changing the content of the storage.

摘要翻译： 公开了一种将数据写入芯片上的第一存储器及其系统的方法。 该方法包括将初始固件存储到芯片上的第二存储器中，通过利用初始固件根据特定数据对第一存储进行编程，以及在特定数据成功后阻止应用于至少部分特定数据的进一步编程操作 存储在第一个存储。 因此，本发明可以节省芯片的外部引脚连接，以防止计算机黑客访问或改变存储器的内容。

公开(公告)号：US07480221B2

公开(公告)日：2009-01-20

申请号：US11092765

申请日：2005-03-30

申请人： Yuan-Chin Liu ,  Ming-Yang Chao

发明人： Yuan-Chin Liu ,  Ming-Yang Chao

IPC分类号： G11B7/00

CPC分类号： G11B7/1267 ,  G11B7/0053

摘要： In a method and apparatus for generating optimum write power, a control unit controls a write voltage generating unit to generate sequentially write voltages of different levels to drive an optical read/write head to generate different write powers so as to write data on a plurality of write intervals of an optical recording medium in sequence. Simultaneously, a detecting and computing circuit detects a peak value, a first level and a second level of a write reflected signal generated by each write interval for computation so as to obtain a first control parameter of each write interval, and detects a peak value, a bottom value and a direct current level of a read reflected signal generated during reading of each write interval for computation so as to obtain a second control parameter of each write interval, thereby generating an optimum write power based on optimal first and second control parameters.

摘要翻译： 在用于产生最佳写入功率的方法和装置中，控制单元控制写入电压产生单元以产生不同电平的顺序写入电压以驱动光学读取/写入头以产生不同的写入功率，以便将数据写入多个 依次写入光学记录介质的间隔。 同时，检测和计算电路检测由用于计算的每个写入间隔产生的写入反射信号的峰值，第一电平和第二电平，以便获得每个写入间隔的第一控制参数，并且检测峰值， 在读取每个写入间隔期间产生的读取反射信号的底部值和直流电平，以便获得每个写入间隔的第二控制参数，从而基于最佳第一和第二控制参数产生最佳写入功率。

公开(公告)号：US07423561B2

公开(公告)日：2008-09-09

申请号：US11758655

申请日：2007-06-05

申请人： Hsin-Cheng Chen ,  Pi-Hai Liu ,  Ming-Yang Chao

发明人： Hsin-Cheng Chen ,  Pi-Hai Liu ,  Ming-Yang Chao

IPC分类号： H03M7/00

CPC分类号： G11B20/1426 ,  G11B2020/1442 ,  G11B2020/1457 ,  G11B2220/2541 ,  G11B2220/2579 ,  H03M5/145

摘要： A modulation method for symbols in a frame of a compact disc includes the steps of receiving a plurality of data words, modulating each data word into a code word of a corresponding data symbol, and providing a plurality of combinations of potential merge bits to be inserted between successive symbols of the frame. At least one combination of candidate merge bits is generated according to the plurality of combinations of potential merge bits, a data symbol immediately preceding the location of the candidate merge bits, and a data symbol immediately succeeding the location of the candidate merge bits. The combination of candidate merge bits which minimizes (optimizes) the absolute cumulative DSV is selected when a subsequent group of possible combinations of candidate merge bits is detected or after a predetermined delay, and the selected combination of candidate merge bits is inserted between the two successive data symbols.

摘要翻译： 在光盘的帧中的符号的调制方法包括以下步骤：接收多个数据字，将每个数据字调制成相应数据符号的码字，并提供要插入的潜在合并位的多个组合 在帧的连续符号之间。 根据潜在的合并位，候选合并位的位置之前的数据符号以及候选合并位的位置之后的数据符号的多个组合，生成候选合并位的至少一个组合。 当检测到候选合并比特的可能组合的后续组或者在预定的延迟之后，选择最小化（优化）绝对累积DSV的候选合并比特的组合，并且将所选择的候选合并比特的组合插入在两个连续的 数据符号。