公开(公告)号：US20130063843A1

公开(公告)日：2013-03-14

申请号：US13227502

申请日：2011-09-08

Applicant: Chia-Hui CHEN ,  Fang-Tsun CHU

Inventor： Chia-Hui CHEN ,  Fang-Tsun CHU

IPC: H02H9/04

CPC classification number: H01L27/0292 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/552 ,  H01L23/60 ,  H01L23/62 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157

Abstract: An integrated circuit structure includes first and second integrated circuit devices disposed on a interposer. Each integrated circuit device has electrostatic discharge (ESD) protection circuitry therein connected to an internal ESD bus. The first and second integrated circuit devices communicate with one another through the interposer. The interposer includes an ESD bus electrically connected to the ESD busses of the first and second integrated circuit devices for providing cross-device ESD protection for the integrated circuit devices.

Abstract translation: 集成电路结构包括设置在插入器上的第一和第二集成电路器件。 每个集成电路器件具有连接到内部ESD总线的静电放电（ESD）保护电路。 第一和第二集成电路器件通过插入器彼此通信。 插入器包括电连接到第一和第二集成电路器件的ESD总线的ESD总线，用于为集成电路器件提供交叉器件ESD保护。

公开(公告)号：US20130093052A1

公开(公告)日：2013-04-18

申请号：US13272389

申请日：2011-10-13

Applicant: Wei Yu MA ,  Kuo-Ji CHEN ,  Fang-Tsun CHU ,  Ta-Pen GUO

Inventor： Wei Yu MA ,  Kuo-Ji CHEN ,  Fang-Tsun CHU ,  Ta-Pen GUO

IPC: H01L27/06 ,  H01L21/768

CPC classification number: H01L27/0266 ,  H01L21/76895 ,  H01L23/5228 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures.

Abstract translation: 本申请公开了一种半导体集成电路，包括其上形成有电气器件的衬底，形成在衬底上的局部互连层，以及形成在局部互连层上的全局互连层。 局部互连层具有第一组导电结构，其布置成在各个电气设备之间，电气设备及其相邻的电气设备之一中，或垂直设备和全局互连层之间电连接。 第一组导电结构中的至少一个被配置为具有大于50欧姆的电阻值。 全局互连层具有布置成经由第一组导电结构电连接电器件的第二组导电结构。