公开(公告)号：US07417278B2

公开(公告)日：2008-08-26

申请号：US11122726

申请日：2005-05-05

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7885

摘要： A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In this manner, a higher coupling ratio is achieved without an increase in the cell size while at the same time alleviating the punchthrough and junction break-down of source region by sharing gate voltage along the side-wall.

摘要翻译： 提供具有能够与电池的浮动栅极三维耦合的三维源的分裂栅极闪存单元及其形成方法。 这是通过首先形成隔离沟槽，用共形氧化物衬里，然后用隔离氧化物填充，然后对其进行蚀刻，以在沟槽的上部形成三维耦合区域。 接下来通过用多晶硅填充沟槽的三维区域并对其进行蚀刻来形成浮栅。 控制栅极通过中间多晶硅氧化物形成在浮动栅上。 浮栅形成延伸到沟槽的三维耦合区域中的支腿，从而提供与源也呈三维区域的三维耦合。 形成第三维的浮动栅的腿或侧壁提供了增加源极和浮动栅极之间的耦合的额外区域。 以这种方式，在不增加电池尺寸的同时实现更高的耦合比，同时通过沿着侧壁共享栅极电压来减轻源极区域的穿通和结断流。

公开(公告)号：US06465841B1

公开(公告)日：2002-10-15

申请号：US09709589

申请日：2000-11-13

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L21/28273 ,  H01L29/42324

摘要： A method is disclosed to form a split-gate flash memory cell having nitride spacers formed on a pad oxide and prior the forming of an inter-poly oxide layer thereover. In this manner, any damage that would normally occur to the inter-poly oxide during the etching of the nitride spacers subsequent to the forming of the inter-poly oxide is avoided. Consequently, the variation in the thickness of the inter-poly oxide due to the unpredictable damage to the underlying spacers is also avoided by reversing the order in which the spacers and the inter-poly oxide are formed, including the forming of the pad oxide first. As a result, variation in the erase speed of the inter-gate flash memory cell is prevented, both for cells fabricated on the same wafer as well as on different wafers on same or different production lines.

摘要翻译： 公开了一种形成具有形成在衬垫氧化物上的氮化物间隔物并且之前形成多晶氧化物层的分裂栅极快闪存储器单元的方法。 以这种方式，避免了在形成多晶硅氧化物之前在氮化物间隔物的蚀刻期间多晶氧化物通常会发生的任何损伤。 因此，通过反转形成间隔物和多晶氧化物的顺序，包括首先形成衬垫氧化物，也可以避免由于对下面的间隔物的不可预测的损伤而导致的多晶氧化物厚度的变化 。 结果，对于在同一晶片上以及相同或不同生产线上的不同晶片上制造的单元，都能够防止栅极间闪存单元的擦除速度的变化。

公开(公告)号：US06380583B1

公开(公告)日：2002-04-30

申请号：US09679512

申请日：2000-10-06

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

IPC分类号： H01L2976

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7885

摘要： A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In this manner, a higher coupling ratio is achieved without an increase in the cell size while at the same time alleviating the punchthrough and junction break-down of source region by sharing gate voltage along the side-wall.

摘要翻译： 提供具有能够与电池的浮动栅极三维耦合的三维源的分裂栅极闪存单元及其形成方法。 这是通过首先形成隔离沟槽，用共形氧化物衬里，然后用隔离氧化物填充，然后对其进行蚀刻，以在沟槽的上部形成三维耦合区域。 接下来通过用多晶硅填充沟槽的三维区域并对其进行蚀刻来形成浮栅。 控制栅极通过中间多晶硅氧化物形成在浮动栅上。 浮栅形成延伸到沟槽的三维耦合区域中的支腿，从而提供与源也呈三维区域的三维耦合。 形成第三维的浮动栅的腿或侧壁提供了增加源极和浮动栅极之间的耦合的额外区域。 以这种方式，在不增加电池尺寸的同时实现更高的耦合比，同时通过沿着侧壁共享栅极电压来减轻源极区域的穿通和结断流。

公开(公告)号：US06333228B1

公开(公告)日：2001-12-25

申请号：US09534160

申请日：2000-03-24

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method is provided to improve the control of bird's beak profile of poly in a split gate flash memory cell. The control of the bird's beak profile is achieved in a first embodiment where the polycrystalline layer of the floating gate is annealed at a high temperature. The annealing promotes small grain size and hence smoother surface in the polysilicon, which in turn promotes sharper poly tip. The smoother poly surface also results in thinner inter-poly between the floating gate and the control gate, which together with the sharp poly tip, enhances the erase speed of the split-gate flash memory cell. In a second embodiment, the performance is further enhanced by providing an amorphous silicon for the floating gate, because the amorphous nature of the silicon yields a very smooth surface. This smooth surface is transferred to the recrystallized state of the silicon layer through annealing. Thus, a good control for the bird's beak is achieved. A sharp and short poly tip then results from a well controlled and well-defined bird's beak. Hence, an enhanced split-gate flash memory cell follows.

摘要翻译： 提供了一种方法来改善分裂门闪存单元中聚鸟的鸟嘴形状的控制。 在第一实施例中实现鸟嘴形状的控制，其中浮栅的多晶层在高温下退火。 退火促进了多晶硅中的小晶粒尺寸和因此更平滑的表面，这又促进了更尖锐的多晶硅尖端。 更平滑的多晶面也导致浮栅和控制栅之间的更薄的多晶硅，其与尖锐的多晶硅尖端一起增强了分离栅闪存单元的擦除速度。 在第二实施例中，通过为浮置栅极提供非晶硅来进一步提高性能，因为硅的无定形性能产生非常光滑的表面。 该光滑表面通过退火转移到硅层的再结晶状态。 因此，可以很好地控制鸟的喙。 然后，一个尖锐和短的多头尖端来自良好控制和明确定义的鸟的喙。 因此，增强的分闸式闪存单元如下。

公开(公告)号：US6067254A

公开(公告)日：2000-05-23

申请号：US314590

申请日：1999-05-19

申请人： Di-Son Kuo ,  Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jack Yeh

发明人： Di-Son Kuo ,  Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jack Yeh

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/3427 ,  G11C16/10

摘要： A method of programming split gate flash memory cells which avoids erroneously programming non selected cells and allows the cell size and the array size to be shrunk below previously realizable limits. For N channel cells with the control gates connected to word lines and drains connected to bit lines a negative voltage is supplied between the non selected word lines and ground potential. For P channel cells with the control gates connected to word lines and drains connected to bit lines a positive voltage is supplied between the non selected word lines and ground potential. This allows the minimum length of the control gate over the channel region to be reduced below previously allowable limits and still prevent programming of non selected cells. This also allows cell size and array size to be reduced.

摘要翻译： 编程分裂栅极闪存单元的方法，其避免错误地编程未选择的单元，并允许单元尺寸和阵列尺寸缩小到先前可实现的极限以下。 对于具有连接到字线的控制栅极和连接到位线的漏极的N沟道单元，在非选择字线和地电位之间提供负电压。 对于具有连接到字线的控制栅极和连接到位线的漏极的P沟道单元，在非选择字线和地电位之间提供正电压。 这允许将通道区域上的控制栅极的最小长度减小到低于先前允许的极限，并且仍然阻止对未选择的单元进行编程。 这也可以减小单元格尺寸和阵列大小。

公开(公告)号：US06355527B1

公开(公告)日：2002-03-12

申请号：US09314588

申请日：1999-05-19

申请人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

发明人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is provided for forming a split-gate flash memory cell having reduced size, increased coupling ratio and improved program speed. A split-gate cell is also provided where the a first polysilicon layer forms the floating gate disposed over an intervening intergate oxide formed over a second polysilicon layer forming the control gate. However, the second polysilicon layer is also formed over the source region and overlying the other otherwise exposed portion of the floating gate such that this additional poly line now shares the voltage between the source and the floating gate, thereby reducing punch-through and junction breakdown voltages. In addition, the presence of another poly wall along the floating gate increases the coupling ratio between the source and the floating gate, which in turn improves program speed of the split-gate flash memory cell.

摘要翻译： 提供了一种用于形成具有减小的尺寸，增加的耦合比和改进的程序速度的分离栅极闪存单元的方法。 还提供了分离栅极单元，其中第一多晶硅层形成布置在形成在形成控制栅极的第二多晶硅层上的中间栅极氧化物上的浮置栅极。 然而，第二多晶硅层也形成在源极区上方并且覆盖浮置栅极的另一个另外暴露的部分，使得该附加多线现在共享源极和浮置栅极之间的电压，从而减少穿通和结击穿 电压。 此外，沿浮置栅极的另一个多壁的存在增加了源极和浮置栅极之间的耦合比，这进而提高了分离栅极闪存单元的编程速度。

公开(公告)号：US06174772B1

公开(公告)日：2001-01-16

申请号：US09347548

申请日：1999-07-06

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L21/28273 ,  H01L29/42324

摘要： A method is disclosed to form a split-gate flash memory cell having nitride spacers formed on a pad oxide and prior the forming of an inter-poly oxide layer thereover. In this manner, any damage that would normally occur to the inter-poly oxide during the etching of the nitride spacers subsequent to the forming of the inter-poly oxide is avoided. Consequently, the variation in the thickness of the inter-poly oxide due to the unpredictable damage to the underlying spacers is also avoided by reversing the order in which the spacers and the inter-poly oxide are formed, including the forming of the pad oxide first. As a result, variation in the erase speed of the inter-gate flash memory cell is prevented, both for cells fabricated on the same wafer as well as on different wafers on same or different production lines.

摘要翻译： 公开了一种形成具有形成在衬垫氧化物上的氮化物间隔物并且之前形成多晶氧化物层的分裂栅极快闪存储器单元的方法。 以这种方式，避免了在形成多晶硅氧化物之前在氮化物间隔物的蚀刻期间多晶氧化物通常会发生的任何损伤。 因此，通过反转形成间隔物和多晶氧化物的顺序，包括首先形成衬垫氧化物，也可以避免由于对下面的间隔物的不可预测的损伤而导致的多晶氧化物厚度的变化 。 结果，对于在同一晶片上以及相同或不同生产线上的不同晶片上制造的单元，都能够防止栅极间闪存单元的擦除速度的变化。

公开(公告)号：US6165845A

公开(公告)日：2000-12-26

申请号：US298931

申请日：1999-04-26

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method is provided to form a sharp poly tip to improve the speed of a split-gate flash memory. The sharp poly tip is provided in place of the conventional gate bird's beak (GBB) because the latter requires the forming of thick poly-oxide which is more and more difficult in the miniaturized circuits of the ultra scale integrated technology. Furthermore, it is well known that GBB encroaches under the gate edge in a split-gate flash and degrades the programmability of submicron memory cells. The sharp poly tip of the invention is provided by forming a tapered floating gate through a high pressure etch such that the tip of the upper edge of the floating gate under the poly oxide is sharper and more robust, and, therefore, less susceptible to damage during the manufacture of the cell. The invention is also directed to a semiconductor device fabricated by the disclosed method.

摘要翻译： 提供了一种形成尖锐的多晶硅尖端以提高分流栅闪存的速度的方法。 提供尖锐的多头尖端来代替常规的门鸟嘴（GBB），因为后者需要形成在超级集成技术的小型化电路中越来越困难的厚的多晶氧化物。 此外，众所周知，GBB在分割门闪存中的栅极边缘下侵入并降低亚微米存储器单元的可编程性。 通过高压蚀刻形成锥形浮栅，使得多晶氧化物下方的浮栅的上边缘的尖端更清晰，更坚固，因此不易受损害，从而提供本发明的尖锐的多尖端 在电池的制造期间。 本发明还涉及通过所公开的方法制造的半导体器件。

公开(公告)号：US07001809B2

公开(公告)日：2006-02-21

申请号：US10119327

申请日：2002-04-09

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7885

摘要： A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In this manner, a higher coupling ratio is achieved without an increase in the cell size while at the same time alleviating the punchthrough and junction break-down of source region by sharing gate voltage along the side-wall.

公开(公告)号：US6127229A

公开(公告)日：2000-10-03

申请号：US301222

申请日：1999-04-29

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： There is presented an improved method of fabricating an EEPROM device with a split gate. In the method, a silicon substrate is provided having spaced and parallel recessed oxide regions that isolate component regions where the oxide regions project above the top surface of the substrate. A thin gate oxide is formed on the substrate, and a first conformal layer is deposited over the gate oxide and projecting oxide regions. The substrate is then chemical-mechanically polished to remove the projections of polysilicon over the oxide regions. A silicon nitride layer is deposited on the resultant planar surface of the polysilicon, and elongated openings formed that will define the position of the floating gates that are perpendicular to the oxide regions. The exposed polysilicon in the openings in the silicon nitride are oxidized down to at least the level of the underlying silicon oxide regions, and the silicon nitride layer removed. The polysilicon layer is then removed using the silicon oxide layer as an etch barrier, and the edge surfaces of the resulting polysilicon floating gates oxidized. A second polysilicon layer is deposited on the substrate and elongated word lines formed that are parallel and partially overlapping the floating gates. Source lines are formed in the substrate, and gate lines are formed that overlie the floating gates.

摘要翻译： 提出了一种用分裂栅极制造EEPROM器件的改进方法。 在该方法中，提供硅衬底，其具有间隔开且平行的凹陷氧化物区域，其隔离氧化物区域突出在衬底的顶表面上方的组分区域。 在衬底上形成薄栅氧化物，并且在栅极氧化物和突出的氧化物区域上沉积第一共形层。 然后将衬底进行化学机械抛光以去除多晶硅在氧化物区域上的突起。 在所形成的多晶硅的平坦表面上沉积氮化硅层，形成将形成垂直于氧化物区域的浮栅的位置的细长开口。 氮化硅中的开口中的暴露的多晶硅被氧化到至少下面的氧化硅区域的水平，并且去除了氮化硅层。 然后使用氧化硅层作为蚀刻阻挡层去除多晶硅层，并且所得多晶硅浮栅的边缘表面被氧化。 第二多晶硅层沉积在衬底上，并且形成平行且部分地与浮动栅极重叠的细长字线。 在衬底中形成源极线，并且形成覆盖浮栅的栅极线。