公开(公告)号：US5716874A

公开(公告)日：1998-02-10

申请号：US603248

申请日：1996-02-20

申请人： Joe Ko ,  Gary Hong ,  Chih-Hung Lin

发明人： Joe Ko ,  Gary Hong ,  Chih-Hung Lin

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A method of fabricating an EPROM memory increases a coupling ratio and reduces lateral diffusion by forming a gate oxide layer and a coupling insulator individually. A substrate is provided with a field oxide layer to isolate a predetermined active area. A gate oxide layer is formed on the substrate. On the field oxide layer and the gate oxide layer, a polysilicon layer is deposited and defined, whereby a portion of this polysilicon layer and gate oxide layer form a gate electrode. Using the gate electrode as a mask, the substrate is implanted with impurities to provide source and drain electrodes. A dielectric layer is formed on polysilicon layer. A contact window (via) is formed in a predetermined area of dielectric layer. An insulator is deposited and defined by etching, on dielectric layer and the contact window. On the insulator and dielectric layer, a metal contact layer is deposited and defined to cover the insulator.

摘要翻译： 制造EPROM存储器的方法通过单独形成栅极氧化物层和耦合绝缘体来增加耦合比并减小横向扩散。 衬底设置有场氧化物层以隔离预定的有效面积。 在衬底上形成栅氧化层。 在场氧化物层和栅极氧化物层上沉积并限定多晶硅层，由此该多晶硅层和栅极氧化物层的一部分形成栅电极。 使用栅电极作为掩模，衬底被注入杂质以提供源极和漏极。 介电层形成在多晶硅层上。 在电介质层的预定区域中形成接触窗（通孔）。 通过在电介质层和接触窗上进行蚀刻来沉积并限定绝缘体。 在绝缘体和电介质层上，沉积和限定金属接触层以覆盖绝缘体。

公开(公告)号：US5882970A

公开(公告)日：1999-03-16

申请号：US552428

申请日：1995-11-03

申请人： Chih-Hung Lin ,  Hwi-Huang Chen ,  Gary Hong ,  Chen-Chiu Hsue

发明人： Chih-Hung Lin ,  Hwi-Huang Chen ,  Gary Hong ,  Chen-Chiu Hsue

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A flash memory cell is fabricated by forming a lightly-doped region with only an implantation procedure to avoid lateral diffusion resulting from an increased overlap between the source region and gate as well as a short channel effect, while surrounding the source region with the lightly-doped region to thereby increase the breakdown voltage between the source region and the substrate.

摘要翻译： 闪存单元是通过仅通过注入步骤形成轻掺杂区域来制造的，以避免由于源区和栅极之间的重叠增加而产生的横向扩散以及短沟道效应，同时围绕源极区域， 从而增加源极区域和衬底之间的击穿电压。

公开(公告)号：US5726081A

公开(公告)日：1998-03-10

申请号：US544659

申请日：1995-10-18

申请人： Chih-Hung Lin ,  Gary Hong

发明人： Chih-Hung Lin ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L29/45 ,  H01L29/49 ,  H01L21/84

CPC分类号： H01L29/66772 ,  H01L29/41783 ,  H01L29/458 ,  H01L29/4908

摘要： In a method for fabricating a ULSI MOSFET with SOI structure, an additional polysilicon layer is used to form polysilicon/metal compound metal contacts on source and drain regions and a gate so as to avoid leakage current and short channel effect problems.

摘要翻译： 在制造具有SOI结构的ULSI MOSFET的方法中，使用附加多晶硅层在源极和漏极区域和栅极上形成多晶硅/金属复合金属触点，以避免漏电流和短沟道效应问题。

公开(公告)号：US5646056A

公开(公告)日：1997-07-08

申请号：US540776

申请日：1995-10-11

申请人： Chih-Hung Lin ,  Hwi-Huang Chen ,  Gary Hong

发明人： Chih-Hung Lin ,  Hwi-Huang Chen ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L21/265

CPC分类号： H01L29/456 ,  H01L29/41775 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/49

摘要： In a method for fabricating a ULSI MOSFET, an additional polysilicon layer is used to form polysilicon/metal compound metal contacts on source and drain regions and a gate so as to avoid leakage current and short channel effect problems.

摘要翻译： 在制造ULSI MOSFET的方法中，使用附加的多晶硅层在源极和漏极区域和栅极上形成多晶硅/金属复合金属触点，以避免漏电流和短沟道效应问题。

公开(公告)号：US6001707A

公开(公告)日：1999-12-14

申请号：US241760

申请日：1999-02-01

申请人： Chih-Hung Lin ,  Gary Hong

发明人： Chih-Hung Lin ,  Gary Hong

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/76237

摘要： A method for forming a shallow trench isolation structure in a substrate includes the steps of forming a doped region around the future top corner regions of a trench. The concentration of dopants inside the doped region increases towards the substrate surface. Thereafter, a trench is formed in the substrate, and then a thermal oxidation operation is carried out. Utilizing the higher oxidizing rate for doped substrate relative to an undoped region, the upper corners of the trench become rounded corners. Subsequently, a liner oxide layer is formed over the substrate surface inside the trench using conventional methods. Finally, insulating material is deposited into the trench to form a trench isolation structure.

摘要翻译： 在衬底中形成浅沟槽隔离结构的方法包括以下步骤：在沟槽的未来顶角区域周围形成掺杂区域。 掺杂区内掺杂剂的浓度朝向衬底表面增加。 之后，在衬底中形成沟槽，然后进行热氧化操作。 利用掺杂衬底相对于未掺杂区域的较高氧化速率，沟槽的上角变成圆角。 随后，使用常规方法在沟槽内的衬底表面上形成衬里氧化物层。 最后，将绝缘材料沉积到沟槽中以形成沟槽隔离结构。

公开(公告)号：US06350677B1

公开(公告)日：2002-02-26

申请号：US09630869

申请日：2000-08-02

申请人： Joe Ko ,  Gary Hong

发明人： Joe Ko ,  Gary Hong

IPC分类号： H01L214763

CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L29/665

摘要： A method of forming a self-aligned silicide layer. A planarization process is performed to form a gate with a planar top surface. Due to the planar top surface of the gate, the reactivity and the uniformity of thickness of the subsequently formed silicide layer on the top surface of the gate are improved, such that the resistance of the silicide is reduced, and the performance of the device is improved.

摘要翻译： 一种形成自对准硅化物层的方法。 进行平面化处理以形成具有平坦顶表面的栅极。 由于栅极的平面顶表面，栅极顶表面上随后形成的硅化物层的反应性和厚度的均匀性得到改善，使得硅化物的电阻降低，并且器件的性能为 改进。

公开(公告)号：US06180471B2

公开(公告)日：2001-01-30

申请号：US09183062

申请日：1998-10-30

申请人： Peter Chang ,  Gary Hong ,  Joe Ko

发明人： Peter Chang ,  Gary Hong ,  Joe Ko

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/7836

摘要： A method of fabricating a high voltage semiconductor device. A semiconductor substrate doped with a first type dopant and comprising a gate is provided. A cap oxide layer is formed on the gate optionally. A first ion implantation with a light second type dopant at a wide angle is performed to form a lightly doped region. A spacer is formed on a side wall of the gate. A second ion implantation with a heavy second type dopant is performed, so that a heavily doped region is formed within the lightly doped region.

摘要翻译： 一种制造高电压半导体器件的方法。 提供掺杂有第一类型掺杂剂并且包括栅极的半导体衬底。 可选地，在栅极上形成帽氧化物层。 进行具有广角的第二种光掺杂剂的第一离子注入以形成轻掺杂区域。 隔板形成在门的侧壁上。 执行具有重的第二类型掺杂剂的第二离子注入，使得在轻掺杂区域内形成重掺杂区域。

公开(公告)号：US5899718A

公开(公告)日：1999-05-04

申请号：US859259

申请日：1997-05-20

申请人： Hwi-Huang Chen ,  Joe Ko ,  Gary Hong

发明人： Hwi-Huang Chen ,  Joe Ko ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A method for fabricating flash memory cells having a DDD structure that prevents leakage current during data erasure, that does not require a high temperature drive-in process, and that easily combines with other logic processes. The method for fabricating the flash memory cells utilizes ion implantation through contact windows to establish heavily doped source and drain regions inside previously formed deeply doped source and drain regions to construct the DDD structure.

摘要翻译： 一种用于制造具有DDD结构的闪存单元的方法，其防止在数据擦除期间的泄漏电流，其不需要高温驱动过程，并且易于与其他逻辑处理相结合。 用于制造闪存单元的方法利用离子注入通过接触窗口在先前形成的深掺杂源极和漏极区域内建立重掺杂的源极和漏极区域以构成DDD结构。

公开(公告)号：US5976935A

公开(公告)日：1999-11-02

申请号：US149587

申请日：1998-09-08

申请人： Ying-Jen Lin ,  Joe Ko ,  Gary Hong

发明人： Ying-Jen Lin ,  Joe Ko ,  Gary Hong

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L21/28273

摘要： A method is provided for fabricating an EEPROM (EEPROM (electrically erasable and programmable read-only memory) device, which can help improve the quality of the tunneling oxide layer in the EEPROM device for reliable operation of the EEPROM device. This method is characterized in that the portion of the tungsten silicide (WSi) layer that is directly laid above the tunneling oxide layer is removed, while still allowing all the other part of the tungsten silicide layer to remain unaltered. As a result, in the subsequent heat-treatment process, the degradation in the quality of the tunneling oxide layer that occurs in the prior art due to the forming of a trapping center therein can be prevented. The tunneling oxide layer is thus more assured in quality, allowing the resultant EEPROM to operate reliably with high performance.

摘要翻译： 提供了一种用于制造EEPROM（EEPROM（电可擦除和可编程只读存储器）器件）的方法，其可以帮助提高EEPROM器件中隧道氧化物层的质量，以使EEPROM器件可靠地工作，该方法的特征在于 直接放置在隧道氧化物层上方的硅化钨（WSi）层的部分被去除，同时仍允许硅化钨层的所有其它部分保持不变，结果，在随后的热处理工艺 可以防止由于在其中形成捕获中心而在现有技术中发生的隧道氧化物层的质量下降，因此隧道氧化物层的质量更加确保，使得所得到的EEPROM能够高可靠地运行 性能。

公开(公告)号：US5350710A

公开(公告)日：1994-09-27

申请号：US080536

申请日：1993-06-24

申请人： Gary Hong ,  Joe Ko

发明人： Gary Hong ,  Joe Ko

IPC分类号： H01L23/485 ,  H01L23/525 ,  H01L27/02 ,  H01L21/14

CPC分类号： H01L24/05 ,  H01L23/5252 ,  H01L27/0251 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3011

摘要： A multi-level conductive interconnection for an integrated circuit with an antifuse device is formed, in and on a silicon substrate, wherein there are large contact pad areas at the periphery of the interconnection. The antifuse device is formed from a thin dielectric between a first and second conductor and is connected to the integrated circuit, and is also connected to a ground reference through a silicon junction in the substrate. The large contact pad area is formed with a layer of metal, and is connected to the integrated circuit through the antifuse device, wherein the antifuse device electrically isolates the contact pad and the integrated circuit to prevent charge build-up during subsequent processing. There is further processing in a plasma environment that would normally produce electrical charge build-up at the gate oxide of the integrated circuit, but wherein the antifuse device prevents charge build-up. A voltage is applied to the antifuse device to create a low impedance element, and formation of the integrated circuit is completed.

摘要翻译： 在硅衬底中和硅衬底上形成用于具有反熔丝装置的集成电路的多级导电互连，其中在互连的周边处存在大的接触焊盘区域。 反熔丝装置由第一和第二导体之间的薄电介质形成，并连接到集成电路，并且还通过衬底中的硅结连接到接地基准。 大接触焊盘区域形成有一层金属，并通过反熔丝装置连接到集成电路，其中反熔丝装置电气隔离接触焊盘和集成电路，以防止后续处理期间的电荷积聚。 在等离子体环境中进一步处理通常会在集成电路的栅极氧化层产生电荷积累，但是其中反熔丝装置防止电荷积聚。 向反熔丝装置施加电压以产生低阻抗元件，并且完成集成电路的形成。