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公开(公告)号：US07177177B2
公开(公告)日：2007-02-13
申请号：US11100893
申请日：2005-04-07
申请人： Ching-Te Kent Chuang , Jae-Joon Kim , Keunwoo Kim
发明人： Ching-Te Kent Chuang , Jae-Joon Kim , Keunwoo Kim
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： An eight transistor static random access memory (SRAM)device includes first and second inverters, a first bit line, a first complement bit line, a pair of write access transistors, and a pair of read access transistors. Each of the first and second inverters includes a respective pair of transistors, and has a respective data node. Each of a first and a second of the access transistors has a source, a drain, a front gate, and a back gate. The first access transistor is coupled to the first bit line, and the second access transistor is coupled to the first complement bit line. The back gate of the first access transistor is coupled to the data node of the first inverter; and the back gate of the second access transistor is coupled to the data node of the second inverter. This increases the difference between the threshold voltages of the first and second access transistors.
摘要翻译： 八晶体管静态随机存取存储器（SRAM）器件包括第一和第二反相器，第一位线，第一补码位线，一对写存取晶体管和一对读存取晶体管。 第一和第二反相器中的每一个包括相应的晶体管对，并具有相应的数据节点。 第一和第二存取晶体管中的每一个具有源极，漏极，前栅极和后栅极。 第一存取晶体管耦合到第一位线，第二存取晶体管耦合到第一补码位线。 第一存取晶体管的背栅极耦合到第一反相器的数据节点; 并且第二存取晶体管的背栅极耦合到第二反相器的数据节点。 这增加了第一和第二存取晶体管的阈值电压之间的差异。
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2.发明申请Methods and Apparatus for Varying a Supply Voltage or Reference Voltage Using Independent Control of Diode Voltage in Asymmetrical Double-Gate Devices 有权使用非对称双栅极器件中二极管电压的独立控制改变电源电压或参考电压的方法和装置公开(公告)号：US20090302929A1
公开(公告)日：2009-12-10
申请号：US12511658
申请日：2009-07-29
IPC分类号： H03K3/01
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
摘要翻译： 提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。 提供由电源电压和参考电压中的一个或多个控制的集成电路。 集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。 独立控制可以包括例如背栅偏置。 独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。
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3.发明授权High-density logic techniques with reduced-stack multi-gate field effect transistors 有权具有减少堆叠多栅极场效应晶体管的高密度逻辑技术公开(公告)号：US07382162B2
公开(公告)日：2008-06-03
申请号：US11181954
申请日：2005-07-14
IPC分类号： H03K19/20 , H03K19/094
CPC分类号： H03K19/0948 , H01L29/78648
摘要： Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.
摘要翻译： 提供了在由逻辑门形成的逻辑电路中采用多栅极场效应晶体管（FETS）的技术。 只有当两个晶体管栅极有效时才导通的双栅极晶体管可以用于减少逻辑门串联或“堆叠”部分所需的器件数量。 可以减小电路面积，提高性能。
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4.发明授权Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices 有权使用不对称双栅极器件中二极管电压的独立控制来改变电源电压或参考电压的方法和装置公开(公告)号：US09076509B2
公开(公告)日：2015-07-07
申请号：US12511666
申请日：2009-07-29
IPC分类号： G11C11/00 , G11C5/14 , G11C11/412 , G11C11/417
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
摘要翻译： 提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。 提供由电源电压和参考电压中的一个或多个控制的集成电路。 集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。 独立控制可以包括例如背栅偏置。 独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。
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5.发明申请HIGH-DENSITY LOGIC TECHNIQUES WITH REDUCED-STACK MULTI-GATE FIELD EFFECT TRANSISTORS 有权具有减少堆叠多栅极场效应晶体管的高密度逻辑技术公开(公告)号：US20100026346A1
公开(公告)日：2010-02-04
申请号：US12102097
申请日：2008-04-14
IPC分类号： H03K19/094 , G06F17/50
CPC分类号： H03K19/0948 , H01L29/78648
摘要： Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.
摘要翻译： 提供了在由逻辑门形成的逻辑电路中采用多栅极场效应晶体管（FETS）的技术。 只有当两个晶体管栅极有效时才导通的双栅极晶体管可以用于减少逻辑门串联或“堆叠”部分所需的器件数量。 可以减小电路面积，提高性能。
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6.发明授权High-density logic techniques with reduced-stack multi-gate field effect transistors 有权具有减少堆叠多栅极场效应晶体管的高密度逻辑技术公开(公告)号：US08030971B2
公开(公告)日：2011-10-04
申请号：US12102097
申请日：2008-04-14
IPC分类号： H03K19/20 , H03K19/094
CPC分类号： H03K19/0948 , H01L29/78648
摘要： Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.
摘要翻译： 提供了在由逻辑门形成的逻辑电路中采用多栅极场效应晶体管（FETS）的技术。 只有当两个晶体管栅极有效时才导通的双栅极晶体管可以用于减少逻辑门串联或“堆叠”部分所需的器件数量。 可以减小电路面积，提高性能。
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公开(公告)号：US20090303778A1
公开(公告)日：2009-12-10
申请号：US12511666
申请日：2009-07-29
IPC分类号： G11C11/00
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
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8.发明授权Computer-readable medium encoding a back-gate controlled asymmetrical memory cell and memory using the cell 失效使用该单元编码背栅控制的非对称存储单元和存储器的计算机可读介质公开(公告)号：US07742327B2
公开(公告)日：2010-06-22
申请号：US12265042
申请日：2008-11-05
申请人： Ching Te Chuang , Jae-Joon Kim , Keunwoo Kim
发明人： Ching Te Chuang , Jae-Joon Kim , Keunwoo Kim
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.
摘要翻译： 为非对称存储单元中的背栅极控制提供技术。 在一个方面，电池包括五个晶体管，并且可以用于静态随机存取存储器（SRAM）应用。 本发明的存储器电路可以包括多个位线结构，与多个位线结构相交以形成多个单元位置的多个字线结构以及位于多个单元位置的多个单元。 每个单元可以在对应的一个字线结构的控制下选择性地耦合到相应的一个位线结构。 每个单元可以包括具有第一和第二场效应晶体管（FETS）的第一反相器和具有与第一反相器交叉耦合以形成存储触发器的第三和第四FET的第二反相器。 第一反相器中的FETS之一可以配置有独立的前门和后门，并且可以用作存取晶体管和其中一个逆变器的一部分。
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9.发明申请COMPUTER-READABLE MEDIUM ENCODING A BACK-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USING THE CELL 失效使用电池编码背栅控制不对称存储单元和存储器的计算机可读介质公开(公告)号：US20090067223A1
公开(公告)日：2009-03-12
申请号：US12265042
申请日：2008-11-05
申请人： Ching Te Chuang , Jae-Joon Kim , Keunwoo Kim
发明人： Ching Te Chuang , Jae-Joon Kim , Keunwoo Kim
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.
摘要翻译： 为非对称存储单元中的背栅极控制提供技术。 在一个方面，电池包括五个晶体管，并且可以用于静态随机存取存储器（SRAM）应用。 本发明的存储器电路可以包括多个位线结构，与多个位线结构相交以形成多个单元位置的多个字线结构以及位于多个单元位置的多个单元。 每个单元可以在对应的一个字线结构的控制下选择性地耦合到相应的一个位线结构。 每个单元可以包括具有第一和第二场效应晶体管（FETS）的第一反相器和具有与第一反相器交叉耦合以形成存储触发器的第三和第四FET的第二反相器。 第一反相器中的FETS之一可以配置有独立的前门和后门，并且可以用作存取晶体管和其中一个逆变器的一部分。
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10.发明授权Computer-readable medium encoding a memory using a back-gate controlled asymmetrical memory cell 失效使用背栅控制的非对称存储单元对存储器进行编码的计算机可读介质公开(公告)号：US07492628B2
公开(公告)日：2009-02-17
申请号：US11933505
申请日：2007-11-01
申请人： Ching-Te Chuang , Jae-Joon Kim , Keunwoo Kim
发明人： Ching-Te Chuang , Jae-Joon Kim , Keunwoo Kim
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： Techniques are provided for a computer-readable medium encoding a memory using a back-gate controlled asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An encoded inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.
摘要翻译： 为使用背栅控制的非对称存储单元编码存储器的计算机可读介质提供技术。 在一个方面，电池包括五个晶体管，并且可以用于静态随机存取存储器（SRAM）应用。 编码的本发明的存储器电路可以包括多个位线结构，与多个位线结构相交以形成多个单元位置的多个字线结构以及位于多个单元位置的多个单元。 每个单元可以在对应的一个字线结构的控制下选择性地耦合到相应的一个位线结构。 每个单元可以包括具有第一和第二场效应晶体管（FETS）的第一反相器和具有与第一反相器交叉耦合以形成存储触发器的第三和第四FET的第二反相器。 第一反相器中的FETS之一可以配置有独立的前门和后门，并且可以用作存取晶体管和其中一个逆变器的一部分。
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