Reconfigurable SIMD coprocessor architecture for sum of absolute differences and symmetric filtering (scalable MAC engine for image processing)
    1.
    发明授权
    Reconfigurable SIMD coprocessor architecture for sum of absolute differences and symmetric filtering (scalable MAC engine for image processing) 有权
    可重构SIMD协处理器架构,用于绝对差和对称滤波(可扩展MAC引擎进行图像处理)

    公开(公告)号:US06526430B1

    公开(公告)日:2003-02-25

    申请号:US09411124

    申请日:1999-10-04

    IPC分类号: G06F738

    摘要: The proposed architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute differences, symmetrical row/column Finite Impulse Response (FIR) filtering with a downsampling (or upsampling) option, row/column Discrete Cosine Transform (DCT)/Inverse Discrete Cosine Transform (IDCT), and generic algebraic functions. The architecture is called IPP, which stands for image processing peripheral, and consists of 8 multiply-accumulate hardware units connected in parallel and routed and multiplexed together. The architecture can be dependent upon a Direct Memory Access (DMA) controller to retrieve and write back data from/to DSP memory without intervention from the DSP core. The DSP can set up the DMA transfer and IPP/DMA synchronization in advance, then go on its own processing task. Alternatively, the DSP can perform the data transfers and synchronization itself by synchronizing with the IPP architecture on these transfers. This architecture implements 2-D filtering, symmetrical filtering, short filters, sum of absolute differences, and mosaic decoding more efficiently than the previously disclosed architectures of the prior art.

    摘要翻译: 所提出的架构被集成到作为协处理器的数字信号处理器(DSP)上,以协助计算绝对差值和对数行/列有限脉冲响应(FIR)滤波与下采样(或上采样)选项行/列 离散余弦变换(DCT)/逆离散余弦变换(IDCT)和通用代数函数。 该架构称为IPP,代表图像处理外围设备,由并行连接并路由和多路复用的8个乘法累加硬件单元组成。 该体系结构可以依赖于直接存储器访问(DMA)控制器来从DSP内存检索和写回数据,而不需要DSP内核的干预。 DSP可以提前设置DMA传输和IPP / DMA同步,然后进行自己的处理任务。 或者,DSP可以通过与这些传输上的IPP架构同步来执行数据传输和同步。 该架构比现有技术的先前公开的架构更有效地实现了二维滤波,对称滤波,短滤波器,绝对差的和以及马赛克解码。

    Multiplexer reconfigurable image processing peripheral having for loop control
    2.
    发明授权
    Multiplexer reconfigurable image processing peripheral having for loop control 有权
    多路复用器可重构图像处理外设具有循环控制

    公开(公告)号:US06530010B1

    公开(公告)日:2003-03-04

    申请号:US09475928

    申请日:1999-12-30

    IPC分类号: G06F1500

    摘要: The proposed hardware architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute differences, symmetrical row/column Finite Impulse Response (FIR) filtering with a downsampling (or upsampling) option, row/column Discrete Cosine Transform (DCT)/Inverse Discrete Cosine Transform (IDCT), and generic algebraic functions. The architecture is called IPP, which stands for image processing peripheral, and consists of 8 hardware multiply-accumulate units connected in parallel and routed and multiplexed together. The architecture can be dependent upon a Direct Memory Access (DMA) controller to retrieve and write back data from/to DSP memory without intervention from the DSP core. The DSP can set up the DMA transfer and IPP/DMA synchronization in advance, then go on its own processing task. Alternatively, the DSP can perform the data transfers and synchronization itself by synchronizing with the IPP architecture on these transfers. This hardware architecture implements 2-D filtering, symmetrical filtering, short filters, sum of absolute differences, and mosaic decoding more quickly(in terms of clock cycles) and efficiently than previously disclosed architectures of the prior art which perform the same operations in software.

    摘要翻译: 所提出的硬件架构被集成到作为协处理器的数字信号处理器(DSP)上,以协助计算绝对差值和对数行/列有限脉冲响应(FIR)滤波与下采样(或上采样)选项,行/ 列离散余弦变换(DCT)/逆离散余弦变换(IDCT)和通用代数函数。 该架构称为IPP,代表图像处理外围设备,由并行连接并路由和复用在一起的8个硬件乘法累加单元组成。 该体系结构可以依赖于直接存储器访问(DMA)控制器来从DSP内存检索和写回数据,而不需要DSP内核的干预。 DSP可以提前设置DMA传输和IPP / DMA同步,然后进行自己的处理任务。 或者,DSP可以通过与这些传输上的IPP架构同步来执行数据传输和同步。 该硬件架构在先前公开的在软件中执行相同操作的现有技术的体系结构中实现了二维滤波,对称滤波,短滤波器,绝对差和和拼接解码的速度更快(在时钟周期方面)。