公开(公告)号：US08901959B2

公开(公告)日：2014-12-02

申请号：US13415946

申请日：2012-03-09

申请人： Chris J. Rebeor ,  Rohit Shetty

发明人： Chris J. Rebeor ,  Rohit Shetty

IPC分类号： H03K19/177

CPC分类号： G06F17/5068 ,  G06F2217/40

摘要： A hybrid IO cell for use with controlled collapse chip connection, wirebond core limited, wirebond IO limited, and wirebond inline chip designs is provided. A method of designing the hybrid IO cell includes designating a technology, determining a minimum pad width of the technology, and determining a minimum pad spacing of the technology. The method also includes determining a width of the hybrid IO cell based on the minimum pad width and the minimum pad spacing, setting a length of the hybrid IO cell equal to the determined width, and storing a definition of the IO cell in a library stored on a computer useable storage medium.

摘要翻译： 提供了一种用于控制崩溃芯片连接，引线键芯限制，引线键盘限制和引线键合线芯片设计的混合IO单元。 设计混合IO单元的方法包括指定技术，确定该技术的最小垫宽度，以及确定该技术的最小垫间距。 该方法还包括基于最小焊盘宽度和最小焊盘间距来确定混合IO单元的宽度，将混合IO单元的长度设置为等于所确定的宽度，以及将IO单元的定义存储在存储的库中 在计算机可用的存储介质上。

公开(公告)号：US06377098B1

公开(公告)日：2002-04-23

申请号：US09556923

申请日：2000-04-21

申请人： Chris J. Rebeor

发明人： Chris J. Rebeor

IPC分类号： H03K3356

CPC分类号： H03K3/356156

摘要： A latch device having a selectable feedback path includes a retaining device and system isolation device. The retaining device retains within the feedback path a logical value to be written out. The logical value is latched during an active clock signal. The system isolation device disconnects the retaining device from the feedback path during a write operation. Then, when the logical value is written out, the system isolation device reconnects the retaining device. Thus, the feedback path of the latch device may be disconnected to allow for a change in the latch state without overdriving a feedback inverter.

摘要翻译： 具有可选择的反馈路径的锁存装置包括保持装置和系统隔离装置。 保持装置在反馈路径内保留要写出的逻辑值。 逻辑值在活动时钟信号期间被锁存。 在写入操作期间，系统隔离设备将保持设备与反馈路径断开连接。 然后，当逻辑值被写出时，系统隔离装置重新连接保持装置。 因此，闩锁装置的反馈路径可以被断开以允许闩锁状态​​的改变而不使反馈逆变器过载。

公开(公告)号：US5030856A

公开(公告)日：1991-07-09

申请号：US347542

申请日：1989-05-04

申请人： Allan H. Dansky ,  Chris J. Rebeor ,  Dennis C. Reedy

发明人： Allan H. Dansky ,  Chris J. Rebeor ,  Dennis C. Reedy

IPC分类号： G11C11/417 ,  G11C11/414 ,  H03K3/353 ,  H03K5/08 ,  H03K19/0175 ,  H03K19/086

CPC分类号： H03K19/017518

摘要： A receiver and level converter circuit is disclosed which may be used, for example, in converting low-level logic or other signals to high-level signals. In one embodiment, the circuit includes a differential amplifier having two feedback loops to provide an output signal having hysteresis, for increased gain, better noise margin and compensation. Each feedback loop includes a nonlinear difference network. In a preferred embodiment, the circuit is implemented in BICMOS technology, uses out-of-phase FETs as pull-down devices, and may be used to convert ECL-level signals to CMOS or BICMOS-level signals.