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公开(公告)号：US20080147888A1
公开(公告)日：2008-06-19
申请号：US11588903
申请日：2006-10-26
IPC分类号： G06F3/00
CPC分类号： G06F12/06
摘要： One exemplary method of assigning addresses in two or more address spaces with address fields of different lengths comprises defining address types, assigning a value to first bits at the high ends of the address fields to identify a first said address type, assigning second bits at the low ends of the address fields to identify addresses of the first said address type, and inserting different numbers of additional bits between the first bits and the second bits in the two or more address spaces.
摘要翻译： 在具有不同长度的地址字段的两个或多个地址空间中分配地址的一种示例性方法包括定义地址类型，将值分配给地址字段的高端的第一位以识别第一所述地址类型，在第 地址字段的低端以标识第一所述地址类型的地址，以及在两个或多个地址空间中的第一位和第二位之间插入不同数量的附加位。
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公开(公告)号：US08661162B2
公开(公告)日：2014-02-25
申请号：US11588903
申请日：2006-10-26
IPC分类号： G06F3/00
CPC分类号： G06F12/06
摘要： One exemplary method of assigning addresses in two or more address spaces with address fields of different lengths comprises defining address types, assigning a value to first bits at the high ends of the address fields to identify a first said address type, assigning second bits at the low ends of the address fields to identify addresses of the first said address type, and inserting different numbers of additional bits between the first bits and the second bits in the two or more address spaces.
摘要翻译： 在具有不同长度的地址字段的两个或多个地址空间中分配地址的一种示例性方法包括定义地址类型，将值分配给地址字段的高端的第一位以识别第一所述地址类型，在第 地址字段的低端以标识第一所述地址类型的地址，以及在两个或多个地址空间中的第一位和第二位之间插入不同数量的附加位。
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公开(公告)号：US20090037668A1
公开(公告)日：2009-02-05
申请号：US11830909
申请日：2007-07-31
申请人： Chris M. GILES , Bryan Hornung
发明人： Chris M. GILES , Bryan Hornung
CPC分类号： G06F12/1441 , G06F12/1491
摘要： A system comprises a plurality of computing nodes and a plurality of separate memory devices. A separate memory device is associated with each computing node. The separate memory devices are configured as partition memory in which memory accesses are interleaved across multiple of such memory devices. A protected portion of the partition memory is reserved for use by complex management (CM) code that coordinates partitions implemented on the system. The protected portion of partition memory is restricted from access by operating systems running in the partitions.
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公开(公告)号：US20090037678A1
公开(公告)日：2009-02-05
申请号：US11868772
申请日：2007-10-08
申请人： Chris M. GILES , Bryan Hornung
发明人： Chris M. GILES , Bryan Hornung
IPC分类号： G06F12/00
CPC分类号： G06F12/1441 , G06F9/5016 , G06F12/1491
摘要： A system comprises a plurality of computing nodes and a plurality of separate memory devices. A separate memory device is associated with each computing node. The separate memory devices are configured as partition memory in which memory accesses are interleaved across multiple of such memory devices. A protected portion of the partition memory is reserved for use by complex management (CM) code that coordinates partitions implemented on the system. The protected portion of partition memory is restricted from access by operating systems running in the partitions.
摘要翻译： 系统包括多个计算节点和多个单独的存储器件。 单独的存储器设备与每个计算节点相关联。 分离的存储器件被配置为分区存储器，其中存储器访问跨多个这样的存储器件交错。 分区存储器的受保护部分保留用于协调在系统上实现的分区的复杂管理（CM）代码。 分区存储器的受保护部分受到在分区中运行的操作系统的访问的限制。
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公开(公告)号：US07818508B2
公开(公告)日：2010-10-19
申请号：US11741453
申请日：2007-04-27
申请人： Bryan Hornung , Erin A. Handgen , Gary Gostin , Craig Warner
发明人： Bryan Hornung , Erin A. Handgen , Gary Gostin , Craig Warner
IPC分类号： G06F13/00
CPC分类号： G06F12/0607 , G06F12/0817 , G06F13/1657
摘要： A computer system, related components such as a processor agent, and related method are disclosed. In at least one embodiment, the computer system includes a first core, at least one memory device including a first memory segment, and a first memory controller coupled to the first memory segment. Further, the computer system includes a fabric and at least one processor agent coupled at least indirectly to the first core and the first memory segment, and also coupled to the fabric. A first memory request of the first core in relation to a first memory location within the first memory segment proceeds to the first memory controller by way of the at least one processor agent and the fabric.
摘要翻译： 公开了一种计算机系统，诸如处理器代理的相关组件和相关方法。 在至少一个实施例中，计算机系统包括第一核心，包括第一存储器段的至少一个存储器设备和耦合到第一存储器段的第一存储器控制器。 此外，计算机系统包括织物和至少一个处理器代理，至少间接耦合到第一核心和第一存储器段，并且还耦合到织物。 相对于第一存储器段内的第一存储器位置的第一存储器的第一存储器请求通过至少一个处理器代理和结构进行到第一存储器控制器。
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6.发明授权Using local storage to handle multiple outstanding requests in a SCI system 有权使用本地存储来处理SCI系统中的多个未完成的请求公开(公告)号：US07117313B2
公开(公告)日：2006-10-03
申请号：US10803289
申请日：2004-03-18
申请人： Bryan Hornung , Bryan Marietta , Robert K. King
发明人： Bryan Hornung , Bryan Marietta , Robert K. King
IPC分类号： G06F12/00
CPC分类号： G06F13/1657
摘要： A SCI controller manages responses and requests between SCI interconnection rings and memory access controllers. The SCI controller includes a request activation queue that stores information about the requests until the SCI rings have the resources to handle the requests. The controller also has a response activation queue that stores information about the responses until the memory access controller is accessible. The queues do not store the request and response packets, but rather store information that is used to construct the request and response packets. The SCI controller also has a contents addressable memory or CAM that checks for an address match between the current requests and responses and previous requests and responses. A table stores more specific information about the previous requests.
摘要翻译： SCI控制器管理SCI互连环和存储器访问控制器之间的响应和请求。 SCI控制器包括一个请求激活队列，用于存储关于请求的信息，直到SCI环有资源来处理请求。 控制器还具有响应激活队列，其存储关于响应的信息，直到存储器访问控制器可访问。 队列不存储请求和响应数据包，而是存储用于构造请求和响应数据包的信息。 SCI控制器还具有内容可寻址存储器或CAM，用于检查当前请求与响应之间的地址匹配以及以前的请求和响应。 表格存储有关先前请求的更多具体信息。
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7.发明授权公开(公告)号：US06684381B1
公开(公告)日：2004-01-27
申请号：US09675725
申请日：2000-09-29
申请人： Lionel Bening , Bryan Hornung , Robert Pflederer
发明人： Lionel Bening , Bryan Hornung , Robert Pflederer
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A method of providing hardware description language-embedded regular expression support for module iteration and interconnection. Regular expressions such as those used in the Perl programming language are used in a preprocessing process to generate instances and interconnections in a hardware description to automate the generation of repetitive code for a Hardware Description Language (HDL). This is accomplished by generating HDL code with embedded regular expressions, analyzing the code to identify the regular expressions and checking to see that the code complies with the HDL grammar rules. A data structure is generated for each module or submodule and these data structures are then elaborated to expand them into the instances and interconnections. A text generator traverses the elaborated data structures and generates HDL compliant text.
摘要翻译： 一种为模块迭代和互连提供硬件描述语言嵌入式正则表达式支持的方法。 用于Perl编程语言的正则表达式用于预处理过程，以在硬件描述中生成实例和互连，以自动生成硬件描述语言（HDL）的重复代码。 这是通过使用嵌入式正则表达式生成HDL代码来实现的，分析代码以识别正则表达式，并检查代码是否符合HDL语法规则。 为每个模块或子模块生成数据结构，然后详细阐述这些数据结构，将其扩展到实例和互连中。 文本生成器遍历详细的数据结构并生成符合HDL的文本。
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公开(公告)号：US06665830B2
公开(公告)日：2003-12-16
申请号：US09773124
申请日：2001-01-31
申请人： Bryan Hornung , Gregory S Palmer , Paul F. Vogel
发明人： Bryan Hornung , Gregory S Palmer , Paul F. Vogel
IPC分类号： G11C2900
CPC分类号： G06F11/1004
摘要： A system for building checksums efficiently builds a checksum of various data values that are stored in different memory units of a computer system. During the checksum build process, data stores to the memory locations storing the various data values are enabled, thereby enabling the checksum to be built without significantly impacting the performance of the computer system.
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公开(公告)号：US06473845B1
公开(公告)日：2002-10-29
申请号：US09675021
申请日：2000-09-28
IPC分类号： G06F1300
CPC分类号： G06F12/0292 , G06F13/1663
摘要： In general, a system and method is provided for dynamically reallocating computer memory. A mapper receives requests to access data. The requests include bus addresses, and the mapper maps the bus addresses to memory unit addresses based on a plurality of mappings maintained by the mapper. The memory unit addresses identify a plurality of memory locations including a destination memory location and a source memory location. Data requested by the requests received by the mapper is accessed based on the memory unit addresses mapped from the bus addresses included in the requests. When desired, a data value from the source memory location is dynamically moved to the destination memory location, and the mappings are updated such that a bus address mapped to a memory unit address identifying the source memory location is instead mapped to a memory unit address identifying the destination memory location.
摘要翻译： 通常，提供用于动态地重新分配计算机存储器的系统和方法。 映射器接收访问数据的请求。 请求包括总线地址，并且映射器基于由映射器维护的多个映射将总线地址映射到存储器单元地址。 存储器单元地址识别包括目的地存储器位置和源存储器位置的多个存储器位置。 基于从请求中包括的总线地址映射的存储器单元地址来访问由映射器接收到的请求所请求的数据。 当需要时，来自源存储器位置的数据值被动态地移动到目的地存储器位置，并且映射被更新，使得映射到标识源存储器位置的存储器单元地址的总线地址被映射到存储器单元地址识别 目的地记忆位置。
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公开(公告)号：US06317857B1
公开(公告)日：2001-11-13
申请号：US09759853
申请日：2001-01-12
申请人： Bryan Hornung , Gregory S Palmer , Paul F. Vogel
发明人： Bryan Hornung , Gregory S Palmer , Paul F. Vogel
IPC分类号： G11C2900
CPC分类号： G06F11/1088 , G06F11/1004
摘要： A system for storing and retrieving data utilizes a plurality of memory units having memory locations for storing data values. A checksum of a plurality of the data values in a particular checksum set is maintained in one of the memory locations. One of the plurality of data values can be recovered by combining each of the remaining plurality of data values with the checksum. After retrieving one of the plurality of data values during the data recovery process, steps are taken to ensure that any further attempts to access the location of the retrieved data value do not cause an update to the checksum. Therefore, the locations storing the data values of the checksum set may be accessed (e.g., read from or written to) during the data recovery process without causing errors to the data recovery process.
摘要翻译： 用于存储和检索数据的系统利用具有用于存储数据值的存储器位置的多个存储器单元。 在特定校验和集合中的多个数据值的校验和被保持在存储器位置之一中。 可以通过将剩余的多个数据值中的每一个与校验和组合来恢复多个数据值中的一个。 在数据恢复过程中检索多个数据值中的一个数据值之后，采取步骤以确保进一步尝试访问检索到的数据值的位置不会对校验和进行更新。 因此，可以在数据恢复处理期间存储存储校验和集合的数据值的位置（例如，从其读取或写入），而不会对数据恢复处理造成错误。
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