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公开(公告)号：US06459397B1
公开(公告)日：2002-10-01
申请号：US09675987
申请日：2000-09-29
IPC分类号： H03M302
摘要： The saturation compensating analog to digital converter has converter circuitry receiving an analog signal and outputting converted data. The converted data from the converter circuitry is processed and filtered to provide a digital data output. The digital data output is received into shift register circuitry before being transmitted for later-stage processing. When the converter circuitry is operating close to a saturated condition, a saturation detector generates a saturation signal. The saturation signal is received at a variable gain circuit which adjusts the gain of the input signal to the converter circuitry. The shift register circuitry also receives the saturation signal and provides an upshift of the digital data to compensate for the associated reduction in input gain provided by the variable gain circuit. In operation, the variable gain circuit is initially set to its maximum output, thus providing the maximum possible input signal to the converter. If a near-saturation conditional is detected, the variable gain circuit is stepped down, and the shift register circuitry provides an associated one bit step up. Such saturation compensation is continued to enable the converter circuitry to operate without saturating.
摘要翻译： 饱和补偿模数转换器具有接收模拟信号并输出转换数据的转换器电路。 来自转换器电路的经转换的数据被处理和滤波以提供数字数据输出。 数字数据输出在发送用于后期处理之前被接收到移位寄存器电路中。 当转换器电路工作在接近饱和状态时，饱和检测器产生饱和信号。 在可变增益电路处接收饱和信号，该可变增益电路调节到转换器电路的输入信号的增益。 移位寄存器电路还接收饱和信号并且提供数字数据的升档以补偿由可变增益电路提供的输入增益的相关联的降低。 在操作中，可变增益电路初始设置为其最大输出，从而为转换器提供最大可能的输入信号。 如果检测到近饱和条件，则可变增益电路被降低，并且移位寄存器电路提供相关的一位加法。 继续这种饱和补偿，使得转换器电路能够在没有饱和的情况下运行。
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公开(公告)号：US09100182B2
公开(公告)日：2015-08-04
申请号：US13358222
申请日：2012-01-25
申请人： Christian Volf Olgaard , Ray Wang
发明人： Christian Volf Olgaard , Ray Wang
CPC分类号： H04L1/244 , H04B7/0413 , H04L1/06 , H04L1/243
摘要： A digital communications test system and method for testing a plurality of devices under test (DUTs) in which multiple sets of a single vector signal analyzer (VSA) and single vector signal generator (VSG) can be used together to perform error vector magnitude (EVM) measurements for one or more DUTs in parallel, including one or more of composite, switched and multiple input multiple output (MIMO) EVM measurements. This allows N pairs of a VSA and VSG to test N DUTs with N×N MIMO in substantially the sane time as a single VSA and VSG pair can test a single DUT, thereby allowing a substantial increase in testing throughput as compared to that possible with only a single VSA and VSG set.
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3.发明授权System and method for synchronized triggering of test equipment for testing MIMO transceivers 有权用于测试MIMO收发器的测试设备的同步触发的系统和方法公开(公告)号：US08774729B2
公开(公告)日：2014-07-08
申请号：US13462141
申请日：2012-05-02
IPC分类号： H04B17/00
CPC分类号： H04B17/0085 , H04B7/0413
摘要： A system and method for testing multiple-input-multiple-output (MIMO) devices under test (DUTs) with multiple radio frequency (RF) signal testers. Each tester receives one or more RF signals from one or more of the DUTs, and the testers are mutually coupled in a ring such that successive ones receive a trigger input signal from an upstream tester and provide a trigger output signal to a downstream tester. Each tester is responsive to its input trigger signal and its one or more RF signals by providing its output trigger signal such that its output trigger signal has an asserted state initiated in response to an assertion of its input trigger signal and a transcending of a predetermined magnitude by at least one of the one or more RF signals.
摘要翻译： 一种用于测试多个射频（RF）信号测试仪的被测试多输入多输出（MIMO）器件（DUT）的系统和方法。 每个测试仪从一个或多个DUT接收一个或多个RF信号，并且测试器在环中相互耦合，使得连续的接收来自上游测试器的触发输入信号并向下游测试器提供触发输出信号。 每个测试器通过提供其输出触发信号来响应于其输入触发信号及其一个或多个RF信号，使得其输出触发信号具有响应于其输入触发信号的断言和超出预定幅度而被启动的有效状态 通过所述一个或多个RF信号中的至少一个。
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公开(公告)号：US08774024B2
公开(公告)日：2014-07-08
申请号：US12943237
申请日：2010-11-10
申请人： Christian Volf Olgaard , Ruizu Wang
发明人： Christian Volf Olgaard , Ruizu Wang
IPC分类号： H04L12/26
摘要： A method and system for testing a wireless data packet transceiver as a device under test (DUT) adapted to operate in conformance with a wireless signal standard such that a transmitted signal, when received by an intended receiver, is to result in a responsive signal transmission acknowledging such signal reception. During testing, responsive signal transmissions, e.g., acknowledgement signals, are withheld by the test system until after a predetermined number of data packets have been captured from the DUT, until a predetermined time interval has passed, or until data packets at a predetermined number of data rates have been captured from the DUT.
摘要翻译： 一种用于测试无线数据分组收发器作为适于根据无线信号标准进行操作的被测设备（DUT）的方法和系统，使得当预期接收机接收到的发射信号将导致响应信号传输 承认这样的信号接收。 在测试期间，由测试系统保留响应信号传输，例如确认信号，直到从DUT被捕获到预定数量的数据分组，直到经过预定的时间间隔，或直到预定数量的 数据速率已从DUT捕获。
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5.发明授权System and method for deterministic testing of packet error rate in electronic devices 有权电子设备中数据包错误率确定性测试的系统和方法公开(公告)号：US08693351B2
公开(公告)日：2014-04-08
申请号：US13191154
申请日：2011-07-26
IPC分类号： H04L12/26
摘要： A method and system for testing packet error rate in electronic devices by transmitting a series of data packets from a testing device to a device under test (DUT) and setting a predefined number of received error-free data packets; evaluating whether a number of data packets from the series of data packets received error-free by the DUT equals the predefined number of received error-free data packets and transmitting additional data packets from the testing device to the DUT, at a power level known to produce zero received-packet errors in a correctly operating DUT, if the number of data packets from the series of data packets received error-free by the DUT does not equal the predefined number of received error-free data packets. Additional possible embodiments include evaluating whether a total number of data packets from the series of data packets and the additional error-free-power-level data packets received error-free by the DUT equals the predefined number of received error-free data packets and transmitting a confirmation data packet to the testing device in response to reception by the DUT of the predefined number of received error-free data packets.
摘要翻译： 一种用于通过从测试设备向被测设备（DUT）发送一系列数据分组并且设置预定数量的接收到的无错误数据分组来测试电子设备中的分组错误率的方法和系统; 评估所述DUT接收的所述一系列数据分组的数据分组是否等于所接收的无错误数据分组的预定数量，并以已知的功率级别从所述测试装置向所述DUT发送附加数据分组 如果由DUT接收到的无错误数据分组的数据分组的数量不等于接收到的无错误数据分组的预定数量，则在正确操作的DUT中产生零接收分组错误。 其他可能的实施例包括评估来自该系列数据分组的数据分组的总数和DUT接收到的无错误功率级数据分组是否等于接收到的无错误数据分组的预定数量，并且发送 响应于DUT接收到预定数量的接收的无错误数据分组，向测试设备发送确认数据分组。
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6.发明授权System and method of maintaining correction of DC offsets in frequency down-converted data signals 有权维持降频转换数据信号中DC偏移校正的系统和方法公开(公告)号：US08537942B2
公开(公告)日：2013-09-17
申请号：US13357370
申请日：2012-01-24
IPC分类号： H04B1/10
CPC分类号： H04L25/061
摘要： Circuitry and method for reduce test time for wireless signal systems by using dynamic adaptive correction of DC offsets generated by the test instrument. The data signal is sampled for downstream processing including during pre-, inter-, or post-packet time intervals where no packet-data signal is occurring and where the device's power amplifier is turned off. The sampled data signal is measured for a DC offset occurring during these inter-packet time gaps. Compensating DC offset values are stored in a table indexed by frequency, gain and temperature range. When a subsequent test is carried out at that frequency, gain, and temperature range, the stored compensation value is used to correct the signal. DC offsets continue to be measured, stored and applied to captured signals, continuously refining the compensation values and decreasing the need for time-intensive calibrations. When a measured DC offset exceeds pre-determined limits, the instrument undergo a calibration step.
摘要翻译： 通过使用由测试仪器产生的直流偏移的动态自适应校正，减少无线信号系统的测试时间的电路和方法。 数据信号被采样用于下游处理，包括在没有分组数据信号出现的前，后或后分组时间间隔以及设备的功率放大器被关闭的情况下。 对于在这些分组间间隙期间发生的DC偏移来测量采样数据信号。 补偿DC偏移值存储在由频率，增益和温度范围索引的表中。 当以该频率，增益和温度范围进行后续测试时，存储的补偿值用于校正信号。 DC补偿继续被测量，存储并应用于捕获的信号，不断地改善补偿值并减少对时间密集校准的需要。 当测量的直流偏移超过预定极限时，仪器将进行校准步骤。
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7.发明授权System and method for using multiple network addresses to establish synchronization of a device under test and test equipment controlling the test 有权使用多个网络地址建立被测设备的同步和控制测试的测试设备的系统和方法公开(公告)号：US08391160B2
公开(公告)日：2013-03-05
申请号：US12791594
申请日：2010-06-01
申请人： Christian Volf Olgaard , Ray Wang
发明人： Christian Volf Olgaard , Ray Wang
IPC分类号： H04J1/16
CPC分类号： H04L43/50
摘要： A system and method for testing a data packet signal transceiver in which multiple network addresses (e.g., media access control, or MAC, addresses) are used to establish synchronization of the device under test and the test equipment controlling the test. In accordance with an exemplary embodiment, synchronization is established using a first MAC address, following which testing is conducted using a second MAC address.
摘要翻译： 用于测试数据分组信号收发器的系统和方法，其中使用多个网络地址（例如，媒体访问控制或MAC地址）来建立被测设备的同步和控制测试的测试设备。 根据示例性实施例，使用第一MAC地址建立同步，随后使用第二MAC地址进行测试。
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8.发明申请SYSTEM AND METHOD FOR SIMULTANEOUS MIMO SIGNAL TESTING WITH SINGLE VECTOR SIGNAL ANALYZER 有权具有单载波信号分析器的同步MIMO信号测试的系统和方法公开(公告)号：US20120269288A1
公开(公告)日：2012-10-25
申请号：US13089945
申请日：2011-04-19
申请人： Christian Volf Olgaard , Ruizu Wang
发明人： Christian Volf Olgaard , Ruizu Wang
CPC分类号： H04L1/24 , H04B7/0413
摘要： Signal conversion circuitry and method for converting a multiple input, multiple output (MIMO) packet data signal transmission to a plurality of complex data samples for processing by shared test equipment, e.g., a single vector signal analyzer (VSA).
摘要翻译： 信号转换电路和用于将多输入多输出（MIMO）分组数据信号传输转换为多个复数数据采样的方法，用于共享测试设备，例如单个矢量信号分析仪（VSA）的处理。
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9.发明授权Digital communications test system for multiple input, multiple output (MIMO) systems 有权用于多输入多输出（MIMO）系统的数字通信测试系统公开(公告)号：US08228087B2
公开(公告)日：2012-07-24
申请号：US12985848
申请日：2011-01-06
申请人： Christian Volf Olgaard , Ray Wang
发明人： Christian Volf Olgaard , Ray Wang
IPC分类号： G01R31/00
CPC分类号： H04L1/244 , H04B7/0413 , H04L1/06 , H04L1/243
摘要： A digital communications test system and method for testing a plurality of devices under test (DUTs) in which multiple sets of a single vector signal analyzer (VSA) and single vector signal generator (VSG) can be used together to perform error vector magnitude (EVM) measurements for one or more DUTs in parallel, including one or more of composite, switched and multiple input multiple output (MIMO) EVM measurements. This allows N pairs of a VSA and VSG to test N DUTs with NxN MIMO in substantially the sane time as a single VSA and VSG pair can test a single DUT, thereby allowing a substantial increase in testing throughput as compared to that possible with only a single VSA and VSG set.
摘要翻译： 一种用于测试多个待测器件（DUT）的数字通信测试系统和方法，其中多组单向量信号分析器（VSA）和单矢量信号发生器（VSG）可以一起用于执行误差矢量幅度（EVM ）测量，包括并行的一个或多个DUT，包括复合，交换和多输入多输出（MIMO）EVM测量中的一个或多个。 这允许N对VSA和VSG在基本上理想的时间内以NxN MIMO测试N个DUT，因为单个VSA和VSG对可以测试单个DUT，从而允许测试吞吐量大大增加，与仅可能的 单VSA和VSG集。
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10.发明授权Digital communications test system for multiple input, multiple output (MIMO) systems 有权用于多输入多输出（MIMO）系统的数字通信测试系统公开(公告)号：US07948254B2
公开(公告)日：2011-05-24
申请号：US12348992
申请日：2009-01-06
申请人： Christian Volf Olgaard , Ray Wang
发明人： Christian Volf Olgaard , Ray Wang
IPC分类号： G01R31/00
CPC分类号： H04L1/244 , H04B7/0413 , H04L1/06 , H04L1/243
摘要： A digital communications test system and method for testing a plurality of devices under test (DUTs) in which multiple sets of a single vector signal analyzer (VSA) and single vector signal generator (VSG) can be used together to perform error vector magnitude (EVM) measurements for one or more DUTs in parallel, including one or more of composite, switched and multiple input multiple output (MIMO) EVM measurements. This allows N pairs of a VSA and VSG to test N DUTs with N×N MIMO in substantially the sane time as a single VSA and VSG pair can test a single DUT, thereby allowing a substantial increase in testing throughput as compared to that possible with only a single VSA and VSG set.
摘要翻译： 一种用于测试多个待测器件（DUT）的数字通信测试系统和方法，其中多组单向量信号分析器（VSA）和单矢量信号发生器（VSG）可以一起用于执行误差矢量幅度（EVM ）测量，包括并行的一个或多个DUT，包括复合，交换和多输入多输出（MIMO）EVM测量中的一个或多个。 这允许N对VSA和VSG在基本上理想的时间内以N×N MIMO测试N个DUT，因为单个VSA和VSG对可以测试单个DUT，从而允许测试吞吐量大大增加， 只有一个VSA和VSG集合。
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