公开(公告)号：US5764954A

公开(公告)日：1998-06-09

申请号：US518515

申请日：1995-08-23

申请人： Christine Marie Fuller ,  Steven Paul Hartman ,  Eric Ernest Millham

发明人： Christine Marie Fuller ,  Steven Paul Hartman ,  Eric Ernest Millham

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5054 ,  G06F17/5068

摘要： In a Field Programmable Gate Array ("FPGA") design system, a configuration is generated. A path of the configuration is selected as a critical path for optimization. The critical path is optimized by rerouting connections between the logical primitives of the critical path. Prior to the rerouting, the logical primitives of the critical path may be optimally placed within the FPGA configuration. Optimal performance of the critical path is thus achieved.

摘要翻译： 在现场可编程门阵列（“FPGA”）设计系统中，生成一个配置。 选择配置的路径作为优化的关键路径。 关键路径通过重新路由关键路径的逻辑基元之间的连接来优化。 在重新路由之前，关键路径的逻辑原语可能被最佳地置于FPGA配置中。 因此实现了关键路径的最佳性能。

公开(公告)号：US5748009A

公开(公告)日：1998-05-05

申请号：US707840

申请日：1996-09-09

申请人： Allan Robert Bertolet ,  Kim P. N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

发明人： Allan Robert Bertolet ,  Kim P. N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

IPC分类号： H03K19/177 ,  H03K19/173

CPC分类号： H03K19/1737

摘要： A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e.g., clock) input available to at least one of the input multiplexers; a flip-flop connected within the logic cell; and internal cell feedback. The preferred method of programming utilizes user-programmed SRAM memory cells.

摘要翻译： 可编程逻辑单元具有四个逻辑门，其中两个可配置。 两个可配置逻辑门位于逻辑单元输入附近。 每个可配置逻辑门具有两个输入，每个输入连接到四个逻辑单元输入之一。 剩余的两个逻辑门接收可配置逻辑门的输出。 提供四个独立的逻辑单元输入节点，每个具有与可编程输入多路复用器相关联的逻辑单元输入节点。 每个输入多路复用器可以具有连接到至少两种类型的互连导体的输入。 该单元还具有两个输出路径，每个输出路径与其相关联，具有独立控制的输出多路复用器。 每个输出多路复用器的输出连接到另一个输出多路复用器的输入端。 附加特征包括具有连接到两个单元输入节点的输入的多路复用器，连接到第三逻辑单元输入节点的选择输入和连接到单元输出节点的输出; 用于至少一个输入多路复用器的系统低偏移数据（例如，时钟）输入; 连接在逻辑单元内的触发器; 和内部单元反馈。 优选的编程方法利用用户编程的SRAM存储单元。

公开(公告)号：US5761078A

公开(公告)日：1998-06-02

申请号：US618060

申请日：1996-03-21

申请人： Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Eric Ernest Millham ,  Gulsun Yasar

发明人： Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Eric Ernest Millham ,  Gulsun Yasar

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A computer implemented method for the automated placement and routing in the design of field programmable gate arrays achieves optimal timing. In a library of primitives and macros from which a designer may choose to implement a given circuit design, at least some of said macros are "semi-hard" macros where direct connections and relative placements are specified while local bus routing is requested in a manner that does not restrict macro placement. A logical netlist containing references to macros and how to connect them together to perform a logical function is first created. The logical netlist is then translated to a physical netlist using a mapper function. This physical netlist for the semi-hard macros specifies what is to be connected but not how. The best place to put each macro on the field programmable gate array is found using a placer function. The placer function thus determines an absolute position of the macros. Pre-defined macro direct connections are routed using a router function. The router function determines an optimal path to connect the semi-hard macros. Finally, a bitstream is generated from placement and routing information developed by the placer and router functions to program the field programmable gate array to perform the netlist logical function.

摘要翻译： 用于现场可编程门阵列设计中的自动放置和布线的计算机实现方法实现了最佳的定时。 在设计者可以选择实现给定电路设计的原语和宏的库中，至少一些所述宏是“半硬”宏，其中指定了直接连接和相对放置，同时以某种方式请求本地总线路由 这不会限制宏放置。 首先创建包含对宏的引用以及如何将它们连接在一起以执行逻辑功能的逻辑网表。 然后使用映射器函数将逻辑网表转换为物理网表。 这个半硬宏的物理网表指定了要连接的内容，但不是如何。 使用放置功能可以找到将每个宏放在现场可编程门阵列上的最佳位置。 因此，放置函数决定宏的绝对位置。 使用路由器功能路由预定义的宏直连。 路由器功能确定连接半硬宏的最佳路径。 最后，由放置器和路由器开发的放置和路由信息生成比特流，以对现场可编程门阵列进行编程以执行网表逻辑功能。

公开(公告)号：US5781032A

公开(公告)日：1998-07-14

申请号：US707839

申请日：1996-09-09

申请人： Allan Robert Bertolet ,  Kim P.N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

发明人： Allan Robert Bertolet ,  Kim P.N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

IPC分类号： H03K19/177 ,  H03K7/38 ,  H03K19/21

CPC分类号： H03K19/1778 ,  H03K19/17728

摘要： A programmable logic cell has four cell input nodes and a plurality of combinational logic circuits. Four inverter circuits are provided for programmably inverting respective input logic signals, each inverter circuit having an inverter input node connected to a respective cell input node for accepting its respective input logic signal therefrom. Each inverter is programmable into a first state wherein a logic signal representing the complement of the input logic signal is provided to the inverter output node, and a second state wherein a logic signal representing the non-complement of the input logic signal is provided to the inverter output node. The inverter circuits buffer their input logic signals in both their first and second states. A first logic gate of the plurality of combinational logic circuits has first and second inputs each connected to a respective output node of one of two of the four inverter circuits, and a second logic gate has first and second inputs each connected to a respective output node of one of the other two of the four inverter circuits. The inverter circuits may be implemented as XNOR gates.

摘要翻译： 可编程逻辑单元具有四个单元输入节点和多个组合逻辑电路。 提供四个逆变器电路用于可编程地反相各个输入逻辑信号，每个反相器电路具有连接到各个单元输入节点的反相器输入节点，用于从其接收其相应的输入逻辑信号。 每个逆变器可编程为第一状态，其中表示输入逻辑信号的补码的逻辑信号被提供给逆变器输出节点，并且第二状态，其中表示输入逻辑信号的非补码的逻辑信号被提供给 逆变器输出节点。 逆变器电路在第一和第二状态下缓冲它们的输入逻辑信号。 多个组合逻辑电路的第一逻辑门具有第一和第二输入，每个连接到四个反相器电路中的两个中的一个的相应输出节点，第二逻辑门具有第一和第二输入，每个连接到相应的输出节点 的四个逆变器电路中的另外两个之一。 逆变器电路可以被实现为XNOR门。

公开(公告)号：US5646546A

公开(公告)日：1997-07-08

申请号：US460481

申请日：1995-06-02

申请人： Allan Robert Bertolet ,  Kim P. N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

发明人： Allan Robert Bertolet ,  Kim P. N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

IPC分类号： H03K19/177 ,  H03K19/173 ,  H03F19/177

CPC分类号： H03K19/1737

摘要： A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e.g., clock) input available to at least one of the input multiplexers; a flip-flop connected within the logic cell; and internal cell feedback. The preferred method of programming utilizes user-programmed SRAM memory cells.

摘要翻译： 可编程逻辑单元具有四个逻辑门，其中两个可配置。 两个可配置逻辑门位于逻辑单元输入附近。 每个可配置逻辑门具有两个输入，每个输入连接到四个逻辑单元输入之一。 剩余的两个逻辑门接收可配置逻辑门的输出。 提供四个独立的逻辑单元输入节点，每个具有与可编程输入多路复用器相关联的逻辑单元输入节点。 每个输入多路复用器可以具有连接到至少两种类型的互连导体的输入。 该单元还具有两个输出路径，每个输出路径与其相关联，具有独立控制的输出多路复用器。 每个输出多路复用器的输出连接到另一个输出多路复用器的输入端。 附加特征包括具有连接到两个单元输入节点的输入的多路复用器，连接到第三逻辑单元输入节点的选择输入和连接到单元输出节点的输出; 用于至少一个输入多路复用器的系统低偏移数据（例如，时钟）输入; 连接在逻辑单元内的触发器; 和内部单元反馈。 编程的首选方法利用用户编程的SRAM存储单元。

公开(公告)号：US5671432A

公开(公告)日：1997-09-23

申请号：US460420

申请日：1995-06-02

申请人： Allan Robert Bertolet ,  Kenneth Ferguson ,  Scott Whitney Gould ,  Eric Ernest Millham ,  Ronald Raymond Palmer ,  Brian Worth ,  Terrance John Zittritsch

发明人： Allan Robert Bertolet ,  Kenneth Ferguson ,  Scott Whitney Gould ,  Eric Ernest Millham ,  Ronald Raymond Palmer ,  Brian Worth ,  Terrance John Zittritsch

IPC分类号： G06F7/00 ,  H03K19/173 ,  H03K19/177 ,  G06F13/20 ,  G06F13/40

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/17704

摘要： A programmable array having programmable logic cells, a programmable interconnect network and a programmable I/O system. Two I/O interfaces are provided for respective logic cells about the perimeter of the array. The I/O interfaces comprise input, output and enable paths. Each of these paths has an associated multiplexer. An I/O routing network is positioned about the perimeter of the array. Conductors connecting the I/O interface multiplexers to the programmable interconnect network also intersect, and can be programmably connected to, buses of the I/O routing network.

摘要翻译： 具有可编程逻辑单元，可编程互连网络和可编程I / O系统的可编程阵列。 为阵列周边的各个逻辑单元提供两个I / O接口。 I / O接口包括输入，输出和使能路径。 这些路径中的每一个具有相关联的多路复用器。 I / O路由网络围绕阵列的周边定位。 将I / O接口多路复用器连接到可编程互连网络的导线也与I / O路由网络的总线相交并且可编程地连接到总线。