公开(公告)号：US6154791A

公开(公告)日：2000-11-28

申请号：US871945

申请日：1997-06-10

申请人： Christopher John Kimble ,  Thomas J. Osten ,  Paul Gary Reuland ,  Daniel Guy Young

发明人： Christopher John Kimble ,  Thomas J. Osten ,  Paul Gary Reuland ,  Daniel Guy Young

IPC分类号： G06F11/20 ,  G06F11/30

CPC分类号： G06F11/201

摘要： A communication system for an array of DASD includes a plurality of loop resiliency circuits and a plurality of selection circuits. The DASD array includes a plurality of DASD slots. Each DASD slot may receive a DASD, and each DASD receives power from a regulator. The loop resiliency circuits form at least a first communication path. Each loop resiliency circuit is associated with one of the DASD slots and selectively includes the associated DASD slot in the first communication path based on a selection signal. The plurality of selection circuits are also associated with one of the DASD slots; and therefore, are also associated with one of the plurality of loop resiliency circuits. Each selection circuit is connected to the associated DASD slot and receives output from the regulator in the associated DASD slot. Based on the regulator output, or a lack thereof, the selection circuit generates a selection signal for the associated loop resiliency circuit. Besides being serially connected to form a single communication path, the loop resiliency circuits can be divided into groups wherein the loop resiliency circuits in each group are serially connected to form a communication path. Separate loop resiliency circuits then selectively connect these communication paths to a main communication path including an initiator. As a further alternative, a second initiator can be selectively placed in one of the communication paths via another loop resiliency circuit.

摘要翻译： 用于DASD阵列的通信系统包括多个环路回弹电路和多个选择电路。 DASD阵列包括多个DASD槽。 每个DASD插槽可以接收DASD，并且每个DASD从调节器接收电力。 环路弹性电路形成至少第一通信路径。 每个回路弹性电路与DASD时隙中的一个相关联，并且基于选择信号选择性地包括第一通信路径中的相关联的DASD时隙。 多个选择电路也与DASD时隙中的一个相关联; 因此也与多个环路回弹电路中的一个相关联。 每个选择电路连接到相关联的DASD插槽，并在相关联的DASD插槽中接收来自稳压器的输出。 基于调节器输出或其缺乏，选择电路产生用于相关联的回路弹性电路的选择信号。 除了串联连接以形成单个通信路径之外，环路弹性电路可以被划分成组，其中每组中的环路弹性电路串联连接以形成通信路径。 然后，单独的回路弹性电路选择性地将这些通信路径连接到包括启动器的主通信路径。 作为另一替代方案，可以经由另一回路弹性电路将第二启动器选择性地置于通信路径之一中。

公开(公告)号：US06334167B1

公开(公告)日：2001-12-25

申请号：US09144593

申请日：1998-08-31

申请人： Edward T. Gerchman ,  Mark C. Gildea ,  William P. Hovis ,  Randall S. Jensen ,  Warren E. Maule ,  Thomas J. Osten ,  Andrew H. Wottreng

发明人： Edward T. Gerchman ,  Mark C. Gildea ,  William P. Hovis ,  Randall S. Jensen ,  Warren E. Maule ,  Thomas J. Osten ,  Andrew H. Wottreng

IPC分类号： G06F1200

CPC分类号： G11C11/406 ,  G11C11/40611 ,  G11C11/40615

摘要： A memory controller, upon detecting an interval of inactivity (that is, no read or write access from a processor or I/O devices with respect to main storage or memory SDRAMs) halts external refresh commands from the processor, and initiates STR mode in main storage to preserve data contents in the memory SDRAMs and to save energy. Then, upon detecting a read or write operation, the memory controller signals main storage to exit STR mode.

摘要翻译： 存储器控制器在检测到不活动的时间间隔（即，没有从处理器或I / O设备相对于主存储器或存储器SDRAM的读取或写入访问）从处理器停止外部刷新命令时，并且主要地发起STR模式 存储以保存存储器SDRAM中的数据内容并节省能量。 然后，当检测到读或写操作时，存储器控制器将主存储器信号退出STR模式。