-
公开(公告)号：US06195775B1
公开(公告)日：2001-02-27
申请号：US09145724
申请日：1998-09-02
IPC分类号： G01R3128
CPC分类号： G01R31/318541
摘要： A boundary configuration (Common Input/output CIO) for Generalized Scan Designs (GSD) in a single clock chip design includes at least one generalized scan design internal latch; a boundary scan clock input to the internal latch; an input/output cell connected to the internal latch; and at least one control line between the internal latch and the input/output cell. The CIO GSD is arranged and configured to operate in various modes including a function mode, a RUNBIST/INTEST/LBIST mode, an EXTEST/WIRETEST mode, a SAMPLE/PRELOAD mode, etc. In a different version, a MUX controller is connected to the internal latch. The MUX controller selects data from one of at least two control lines and sending the selected data to at least one internal logic unit of the chip for a test operation.
摘要翻译： 在单时钟芯片设计中的通用扫描设计（GSD）的边界配置（公共输入/输出CIO）包括至少一个通用扫描设计内部锁存器; 边界扫描时钟输入到内部锁存器; 连接到内部锁存器的输入/输出单元; 以及内部锁存器和输入/输出单元之间的至少一个控制线。 CIO GSD被布置和配置为以各种模式操作，包括功能模式，RUNBIST / INTEST / LBIST模式，EXTEST / WIRETEST模式，SAMPLE / PRELOAD模式等。在不同的版本中，MUX控制器连接到 内部闩锁。 MUX控制器从至少两条控制线之一中选择数据，并将所选择的数据发送到用于测试操作的芯片的至少一个内部逻辑单元。
-
公开(公告)号：US5804998A
公开(公告)日：1998-09-08
申请号：US772879
申请日：1996-12-26
IPC分类号： G11C7/10 , H03K19/0185 , G11C8/00
CPC分类号： H03K19/018521 , G11C7/1051 , G11C7/1078
摘要： The present invention is a driver circuit for interfacing electronic components which have different supply voltages. The driver circuit includes a source terminal for receiving a source voltage, an output terminal connected to an off-chip electronic component, and a pull up circuit disposed between the source and output terminals for providing a field effect controlled current path between the source terminal and the output terminal. The pull up circuit includes a first transistor in series with a second transistor, the second transistor providing overvoltage stress relief for the first transistor.
摘要翻译： 本发明是用于接口具有不同电源电压的电子部件的驱动电路。 驱动器电路包括用于接收源极电压的源极端子，连接到片外电子部件的输出端子和设置在源极和输出端子之间的上拉电路，用于在源极端子和源极端子之间提供场效应控制电流路径 输出端子。 上拉电路包括与第二晶体管串联的第一晶体管，第二晶体管为第一晶体管提供过压应力释放。
-
3.发明授权Method and apparatus for implementing power control in multi-voltage I/O circuits 失效用于在多电压I / O电路中实现功率控制的方法和装置公开(公告)号：US06937060B2
公开(公告)日：2005-08-30
申请号：US10760430
申请日：2004-01-20
IPC分类号： H03K19/00 , H03K19/003
CPC分类号： H03K19/0016
摘要： A method and apparatus are provided for implementing power control in multi-voltage input/output (I/O) circuits. First current biasing devices are provided for creating a first constant bias current. Second current biasing devices are provided for creating a second bias current. The second current biasing devices are activated at a first voltage and are deactivated at a second voltage. The first voltage is less than the second voltage.
摘要翻译： 提供一种用于在多电压输入/输出（I / O）电路中实现功率控制的方法和装置。 提供第一电流偏置器件用于产生第一恒定偏置电流。 提供第二电流偏置装置用于产生第二偏置电流。 第二电流偏置装置在第一电压下被激活，并且在第二电压下被去激活。 第一电压小于第二电压。
-
公开(公告)号：US06476659B1
公开(公告)日：2002-11-05
申请号：US09990467
申请日：2001-11-21
IPC分类号： H03K190185
CPC分类号： H03K5/151 , H03K19/018521
摘要： A high speed voltage level shifter and phase splitter circuit is provided. The voltage level shifter and phase splitter circuit includes an input signal and a first input inverter stage that receives the input signal and provides an inverted delayed out of phase signal to the input signal. A buffer stage receives the input signal and provides a buffered delayed in phase signal to the input signal. A first constant current source is coupled between the first input inverter stage and the buffer stage. A first output inverter stage is coupled to the first constant current source and provides a voltage level shifted and out of phase signal to the input signal. A second constant current source is coupled between the first input inverter stage and the buffer stage having an opposite polarity as the first constant current source. A second output inverter stage is coupled to the second constant current source and providing a voltage level shifted and in phase signal to the input signal.
摘要翻译： 提供了高速电压电平移位器和分相器电路。 电压电平移位器和分相器电路包括输入信号和第一输入反相器级，其接收输入信号并向输入信号提供反相延迟异相信号。 缓冲级接收输入信号并向输入信号提供缓冲的相位相位信号。 第一恒流源耦合在第一输入反相器级与缓冲级之间。 第一输出反相器级耦合到第一恒流源，并向输入信号提供电压电平移位和异相信号。 第二恒定电流源耦合在具有与第一恒定电流源相反的极性的第一输入反相器级与缓冲级之间。 第二输出反相器级耦合到第二恒流源，并向输入信号提供电压电平移位和同相信号。
-
公开(公告)号：US06239617B1
公开(公告)日：2001-05-29
申请号：US09434861
申请日：1999-11-04
IPC分类号： H03K190175
CPC分类号： H03K19/0005
摘要： A mixed voltage output driver includes an output sensing circuit that senses an output voltage at an output terminal and generates a voltage signal that corresponds to a voltage level at the output terminal. Next, an impedance selection circuit receives the voltage signal and generates a control signal in response to the output voltage having a higher logical uplevel than the mixed voltage output driver. The control signal is then received by an adjustable drive impedance circuit that is also coupled to an input terminal of the mixed voltage output driver and, in response thereto, the adjustable drive impedance circuit modifies an output drive impedance of the mixed voltage output driver. In another advantageous embodiment, the mixed voltage output driver only determines if the output voltage at the output terminal is at a logical uplevel before adjusting the output drive impedance.
摘要翻译： 混合电压输出驱动器包括输出感测电路，其感测输出端子处的输出电压并产生对应于输出端子处的电压电平的电压信号。 接下来，阻抗选择电路接收电压信号，并响应于具有比混合电压输出驱动器更高的逻辑高电平的输出电压产生控制信号。 然后，控制信号被可调驱动阻抗电路接收，该可调驱动阻抗电路也耦合到混合电压输出驱动器的输入端，并且响应于此，可调驱动阻抗电路修改混合电压输出驱动器的输出驱动阻抗。 在另一个有利的实施例中，混合电压输出驱动器仅在调整输出驱动阻抗之前确定输出端子处的输出电压是否处于逻辑上限。
-
6.发明授权Communication system for an array of direct access storage devices (DASD) that provides for bypassing one or multiple DASD 失效用于提供绕过一个或多个DASD的直接访问存储设备（DASD）阵列的通信系统
公开(公告)号：US6154791A
公开(公告)日：2000-11-28
申请号：US871945
申请日：1997-06-10
CPC分类号： G06F11/201
摘要： A communication system for an array of DASD includes a plurality of loop resiliency circuits and a plurality of selection circuits. The DASD array includes a plurality of DASD slots. Each DASD slot may receive a DASD, and each DASD receives power from a regulator. The loop resiliency circuits form at least a first communication path. Each loop resiliency circuit is associated with one of the DASD slots and selectively includes the associated DASD slot in the first communication path based on a selection signal. The plurality of selection circuits are also associated with one of the DASD slots; and therefore, are also associated with one of the plurality of loop resiliency circuits. Each selection circuit is connected to the associated DASD slot and receives output from the regulator in the associated DASD slot. Based on the regulator output, or a lack thereof, the selection circuit generates a selection signal for the associated loop resiliency circuit. Besides being serially connected to form a single communication path, the loop resiliency circuits can be divided into groups wherein the loop resiliency circuits in each group are serially connected to form a communication path. Separate loop resiliency circuits then selectively connect these communication paths to a main communication path including an initiator. As a further alternative, a second initiator can be selectively placed in one of the communication paths via another loop resiliency circuit.
摘要翻译： 用于DASD阵列的通信系统包括多个环路回弹电路和多个选择电路。 DASD阵列包括多个DASD槽。 每个DASD插槽可以接收DASD，并且每个DASD从调节器接收电力。 环路弹性电路形成至少第一通信路径。 每个回路弹性电路与DASD时隙中的一个相关联，并且基于选择信号选择性地包括第一通信路径中的相关联的DASD时隙。 多个选择电路也与DASD时隙中的一个相关联; 因此也与多个环路回弹电路中的一个相关联。 每个选择电路连接到相关联的DASD插槽，并在相关联的DASD插槽中接收来自稳压器的输出。 基于调节器输出或其缺乏，选择电路产生用于相关联的回路弹性电路的选择信号。 除了串联连接以形成单个通信路径之外，环路弹性电路可以被划分成组，其中每组中的环路弹性电路串联连接以形成通信路径。 然后，单独的回路弹性电路选择性地将这些通信路径连接到包括启动器的主通信路径。 作为另一替代方案，可以经由另一回路弹性电路将第二启动器选择性地置于通信路径之一中。
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.017 秒)
