公开(公告)号：US08725993B2

公开(公告)日：2014-05-13

申请号：US13032737

申请日：2011-02-23

申请人： Christopher M. Abernathy ,  Mary D. Brown ,  Susan E. Eisen ,  James A. Kahle ,  Hung Q. Le ,  Dung Q. Nguyen

发明人： Christopher M. Abernathy ,  Mary D. Brown ,  Susan E. Eisen ,  James A. Kahle ,  Hung Q. Le ,  Dung Q. Nguyen

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/30101 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/461

摘要： Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.

摘要翻译： 可以使用各种系统，过程，产品和技术来管理线程转换。 在特定实现中，用于管理线程转换的系统和过程可以包括确定要对两个数据寄存器组的相对使用进行转换的能力，并且基于转换确定来确定是否将线程数据移入 至少一个数据寄存器设置为二级寄存器。 系统和过程还可以包括基于移动确定将线程数据从至少一个数据寄存器集合移动到第二级寄存器的能力。

公开(公告)号：US20120216004A1

公开(公告)日：2012-08-23

申请号：US13032737

申请日：2011-02-23

申请人： Christopher M. Abernathy ,  Mary D. Brown ,  Susan E. Eisen ,  James A. Kahle ,  Hung Q. Le ,  Dung Q. Nguyen

发明人： Christopher M. Abernathy ,  Mary D. Brown ,  Susan E. Eisen ,  James A. Kahle ,  Hung Q. Le ,  Dung Q. Nguyen

IPC分类号： G06F12/02

CPC分类号： G06F9/30101 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/461

摘要： Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.

摘要翻译： 可以使用各种系统，过程，产品和技术来管理线程转换。 在特定实现中，用于管理线程转换的系统和过程可以包括确定要对两个数据寄存器组的相对使用进行转换的能力，并且基于转换确定来确定是否将线程数据移入 至少一个数据寄存器设置为二级寄存器。 系统和过程还可以包括基于移动确定将线程数据从至少一个数据寄存器集合移动到第二级寄存器的能力。

公开(公告)号：US08631223B2

公开(公告)日：2014-01-14

申请号：US12778235

申请日：2010-05-12

申请人： Christopher M. Abernathy ,  Mary D. Brown ,  Hung Q. Le ,  Dung Q. Nguyen

发明人： Christopher M. Abernathy ,  Mary D. Brown ,  Hung Q. Le ,  Dung Q. Nguyen

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30138 ,  G06F9/384

摘要： A processor includes an instruction sequencing unit, execution unit, and multi-level register file including a first level register file having a lower access latency and a second level register file having a higher access latency. Responsive to the processor processing a second instruction in a transactional code section to obtain as an execution result a second register value of the logical register, the mapper moves a first register value of the logical register to the second level register file, places the second register value in the first level register file, marks the second register value as speculative, and replaces a first mapping for the logical register with a second mapping. Responsive to unsuccessful termination of the transactional code section, the mapper designates the second register value in the first level register file as invalid so that the first register value in the second level register file becomes the working value.

摘要翻译： 处理器包括指令排序单元，执行单元和多级寄存器文件，其包括具有较低访问延迟的第一级寄存器文件和具有较高访问延迟的第二级寄存器文件。 响应于处理器处理事务代码部分中的第二指令以获得逻辑寄存器的第二寄存器值作为执行结果，映射器将逻辑寄存器的第一寄存器值移动到第二级寄存器堆，将第二寄存器 在第一级寄存器文件中的值，将第二寄存器值标记为推测，并用第二映射替换逻辑寄存器的第一映射。 响应于事务代码段的不成功终止，映射器将第一级寄存器文件中的第二寄存器值指定为无效，使得第二级寄存器文件中的第一寄存器值变为工作值。

公开(公告)号：US08661228B2

公开(公告)日：2014-02-25

申请号：US13448024

申请日：2012-04-16

申请人： Christopher M. Abernathy ,  Mary D. Brown ,  Hung Q. Le ,  Dung Q. Nguyen

发明人： Christopher M. Abernathy ,  Mary D. Brown ,  Hung Q. Le ,  Dung Q. Nguyen

IPC分类号： G06F9/34

CPC分类号： G06F9/3851 ,  G06F9/30138

摘要： A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a first level register file having lower access latency and a second level register file having higher access latency. Each of the first and second level register files includes a plurality of physical registers for holding operands that is concurrently shared by a plurality of threads. The processor further includes a mapper that, at dispatch of an instruction specifying a source logical register from the instruction fetch unit to the issue queue, initiates a swap of a first operand associated with the source logical register that is in the second level register file with a second operand held in the first level register file. The issue queue, following the swap, issues the instruction to the execution unit for execution.

公开(公告)号：US08661227B2

公开(公告)日：2014-02-25

申请号：US12884411

申请日：2010-09-17

申请人： Christopher M. Abernathy ,  Mary D. Brown ,  Hung Q. Le ,  Dung Q. Nguyen

发明人： Christopher M. Abernathy ,  Mary D. Brown ,  Hung Q. Le ,  Dung Q. Nguyen

IPC分类号： G06F9/34

CPC分类号： G06F9/3851 ,  G06F9/30138

摘要： A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a first level register file having lower access latency and a second level register file having higher access latency. Each of the first and second level register files includes a plurality of physical registers for holding operands that is concurrently shared by a plurality of threads. The processor further includes a mapper that, at dispatch of an instruction specifying a source logical register from the instruction fetch unit to the issue queue, initiates a swap of a first operand associated with the source logical register that is in the second level register file with a second operand held in the first level register file. The issue queue, following the swap, issues the instruction to the execution unit for execution.

摘要翻译： 处理器包括指令提取单元，耦合到指令获取单元的发行队列，耦合到发行队列的执行单元，以及包括具有较低访问延迟的第一级寄存器文件和第二级寄存器文件的多级寄存器文件 具有更高的访问延迟。 第一级和第二级寄存器文件中的每一个包括用于保持多个线程同时共享的操作数的多个物理寄存器。 处理器还包括映射器，在从指令获取单元向发布队列调度指定源逻辑寄存器的指令时，启动与第二级寄存器文件中的源逻辑寄存器相关联的第一操作数的交换， 在第一级寄存器文件中保存的第二个操作数。 在交换之后的问题队列向执行单元发出指令以执行。

公开(公告)号：US10067765B2

公开(公告)日：2018-09-04

申请号：US13470386

申请日：2012-05-14

申请人： Susan E. Eisen ,  Hung Q. Le ,  Bryan J. Lloyd ,  Dung Q. Nguyen ,  David S. Ray ,  Benjamin W. Stolt ,  Shih-Hsiung S. Tung

发明人： Susan E. Eisen ,  Hung Q. Le ,  Bryan J. Lloyd ,  Dung Q. Nguyen ,  David S. Ray ,  Benjamin W. Stolt ,  Shih-Hsiung S. Tung

IPC分类号： G06F9/38 ,  G06F9/30

摘要： Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.

公开(公告)号：US20130305022A1

公开(公告)日：2013-11-14

申请号：US13470386

申请日：2012-05-14

申请人： Susan E. Eisen ,  Hung Q. Le ,  Bryan J. Lloyd ,  Dung Q. Nguyen ,  David S. Ray ,  Benjamin W. Stolt ,  Shih-Hsiung S. Tung

发明人： Susan E. Eisen ,  Hung Q. Le ,  Bryan J. Lloyd ,  Dung Q. Nguyen ,  David S. Ray ,  Benjamin W. Stolt ,  Shih-Hsiung S. Tung

IPC分类号： G06F9/312

CPC分类号： G06F9/30087 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/3861

摘要： Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.

摘要翻译： 在处理器中提供用于执行比先前调度的同步（sync）指令更年轻的指令的机制。 处理器的指令定序器单元调度同步指令。 同步指令被发送到处理器外部的一个或多个设备的嵌套。 指令定序器单元在调度同步指令之后调度后续指令。 调度同步指令后的后续指令的调度是在收到来自嵌套的同步确认响应之前执行的。 指令定序器单元基于后续指令的完成是否依赖于从嵌套接收到同步确认和完成同步指令而执行后续指令的完成。

公开(公告)号：US07278011B2

公开(公告)日：2007-10-02

申请号：US10821054

申请日：2004-04-08

申请人： Susan E. Eisen ,  Hung Q. Le ,  David A. Luick ,  Dung Q. Nguyen

发明人： Susan E. Eisen ,  Hung Q. Le ,  David A. Luick ,  Dung Q. Nguyen

IPC分类号： G06F9/44

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3857

摘要： A method, completion table and processor for tracking a larger number of outstanding instructions. The completion table may include a plurality of entries where each entry tracks a consecutive number of outstanding instructions. Each entry may be configured to store an instruction address and an identification of a first of the consecutive number of outstanding instructions. By being able to track a consecutive number of outstanding instructions, such as the length of a cache line, in each entry in the completion table by only storing the instruction address and identification of the first of the consecutive number of outstanding instruction in that entry, the completion table may be able to track a larger number of outstanding instruction without increasing its size.

摘要翻译： 一种用于跟踪大量未完成指令的方法，完成表和处理器。 完成表可以包括多个条目，其中每个条目跟踪连续数量的未完成指令。 每个条目可以被配置为存储指令地址和连续数量的未完成指令中的第一个的标识。 通过在该条目中仅存储指令地址和连续数目的未完成指令的第一个的标识，能够跟踪连续数量的未完成指令，例如高速缓存行的长度，在完成表中的每个条目中， 完成表可能能够跟踪大量未完成的指令而不增加其大小。

公开(公告)号：US20110302392A1

公开(公告)日：2011-12-08

申请号：US12793718

申请日：2010-06-04

申请人： Christopher M. Abernathy ,  Hung Q. Le ,  Dung Q. Nguyen ,  Benjamin W. Stolt

发明人： Christopher M. Abernathy ,  Hung Q. Le ,  Dung Q. Nguyen ,  Benjamin W. Stolt

IPC分类号： G06F9/30

CPC分类号： G06F9/3804 ,  G06F9/30 ,  G06F9/3851 ,  G06F9/3857

摘要： A method and apparatus for tracking instructions in a processor. A completion unit in the processor receives an instruction group to add to a table to form a received instruction group. In response to receiving the received instruction group, the completion unit determines whether an entry is present that contains a previously stored instruction group in a first location and has space for storing the received instruction group. In response to the entry being present, the completion unit stores the received instruction group in a second location in the entry to form a stored instruction group.

摘要翻译： 一种用于跟踪处理器中的指令的方法和装置。 处理器中的完成单元接收到添加到表中以形成接收到的指令组的指令组。 响应于接收到接收到的指令组，完成单元确定是否存在包含在第一位置中的先前存储的指令组的条目，并且具有用于存储接收到的指令组的空间。 响应于存在的条目，完成单元将接收到的指令组存储在条目中的第二位置，以形成存储的指令组。

公开(公告)号：US08037366B2

公开(公告)日：2011-10-11

申请号：US12409981

申请日：2009-03-24

申请人： Christopher M. Abernathy ,  Mary D. Brown ,  Dung Q. Nguyen ,  Todd A. Venton

发明人： Christopher M. Abernathy ,  Mary D. Brown ,  Dung Q. Nguyen ,  Todd A. Venton

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3885 ,  G06F11/0721

摘要： A mechanism is provided for issuing instructions. An instruction dispatch unit receives an instruction for dispatch to one of a plurality of execution units. The instruction dispatch unit analyzes a tag register to determine whether a previous tag associated with a previous instruction has been stored in the tag register. Responsive to the previous tag associated with the previous instruction failing to be stored in the tag register, the instruction dispatch unit storing a tag corresponding to the instruction in the tag register. The instruction dispatch unit dispatches the instruction to an issue queue for issue to the one of the plurality of execution units.

摘要翻译： 提供了发出指令的机制。 指令调度单元接收用于发送到多个执行单元之一的指令。 指令调度单元分析标签寄存器以确定与先前指令相关联的先前标签是否已经存储在标签寄存器中。 指令调度单元响应于与先前指令相关联的先前的标签不能存储在标签寄存器中，存储与标签寄存器中的指令相对应的标签。 指令调度单元将指令发送到多个执行单元中的一个执行单元。