公开(公告)号：US07278011B2

公开(公告)日：2007-10-02

申请号：US10821054

申请日：2004-04-08

申请人： Susan E. Eisen ,  Hung Q. Le ,  David A. Luick ,  Dung Q. Nguyen

发明人： Susan E. Eisen ,  Hung Q. Le ,  David A. Luick ,  Dung Q. Nguyen

IPC分类号： G06F9/44

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3857

摘要： A method, completion table and processor for tracking a larger number of outstanding instructions. The completion table may include a plurality of entries where each entry tracks a consecutive number of outstanding instructions. Each entry may be configured to store an instruction address and an identification of a first of the consecutive number of outstanding instructions. By being able to track a consecutive number of outstanding instructions, such as the length of a cache line, in each entry in the completion table by only storing the instruction address and identification of the first of the consecutive number of outstanding instruction in that entry, the completion table may be able to track a larger number of outstanding instruction without increasing its size.

摘要翻译： 一种用于跟踪大量未完成指令的方法，完成表和处理器。 完成表可以包括多个条目，其中每个条目跟踪连续数量的未完成指令。 每个条目可以被配置为存储指令地址和连续数量的未完成指令中的第一个的标识。 通过在该条目中仅存储指令地址和连续数目的未完成指令的第一个的标识，能够跟踪连续数量的未完成指令，例如高速缓存行的长度，在完成表中的每个条目中， 完成表可能能够跟踪大量未完成的指令而不增加其大小。

公开(公告)号：US08725993B2

公开(公告)日：2014-05-13

申请号：US13032737

申请日：2011-02-23

申请人： Christopher M. Abernathy ,  Mary D. Brown ,  Susan E. Eisen ,  James A. Kahle ,  Hung Q. Le ,  Dung Q. Nguyen

发明人： Christopher M. Abernathy ,  Mary D. Brown ,  Susan E. Eisen ,  James A. Kahle ,  Hung Q. Le ,  Dung Q. Nguyen

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/30101 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/461

摘要： Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.

摘要翻译： 可以使用各种系统，过程，产品和技术来管理线程转换。 在特定实现中，用于管理线程转换的系统和过程可以包括确定要对两个数据寄存器组的相对使用进行转换的能力，并且基于转换确定来确定是否将线程数据移入 至少一个数据寄存器设置为二级寄存器。 系统和过程还可以包括基于移动确定将线程数据从至少一个数据寄存器集合移动到第二级寄存器的能力。

公开(公告)号：US10067765B2

公开(公告)日：2018-09-04

申请号：US13470386

申请日：2012-05-14

申请人： Susan E. Eisen ,  Hung Q. Le ,  Bryan J. Lloyd ,  Dung Q. Nguyen ,  David S. Ray ,  Benjamin W. Stolt ,  Shih-Hsiung S. Tung

发明人： Susan E. Eisen ,  Hung Q. Le ,  Bryan J. Lloyd ,  Dung Q. Nguyen ,  David S. Ray ,  Benjamin W. Stolt ,  Shih-Hsiung S. Tung

IPC分类号： G06F9/38 ,  G06F9/30

摘要： Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.

公开(公告)号：US20130305022A1

公开(公告)日：2013-11-14

申请号：US13470386

申请日：2012-05-14

申请人： Susan E. Eisen ,  Hung Q. Le ,  Bryan J. Lloyd ,  Dung Q. Nguyen ,  David S. Ray ,  Benjamin W. Stolt ,  Shih-Hsiung S. Tung

发明人： Susan E. Eisen ,  Hung Q. Le ,  Bryan J. Lloyd ,  Dung Q. Nguyen ,  David S. Ray ,  Benjamin W. Stolt ,  Shih-Hsiung S. Tung

IPC分类号： G06F9/312

CPC分类号： G06F9/30087 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/3861

摘要： Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.

摘要翻译： 在处理器中提供用于执行比先前调度的同步（sync）指令更年轻的指令的机制。 处理器的指令定序器单元调度同步指令。 同步指令被发送到处理器外部的一个或多个设备的嵌套。 指令定序器单元在调度同步指令之后调度后续指令。 调度同步指令后的后续指令的调度是在收到来自嵌套的同步确认响应之前执行的。 指令定序器单元基于后续指令的完成是否依赖于从嵌套接收到同步确认和完成同步指令而执行后续指令的完成。

公开(公告)号：US20120216004A1

公开(公告)日：2012-08-23

申请号：US13032737

申请日：2011-02-23

申请人： Christopher M. Abernathy ,  Mary D. Brown ,  Susan E. Eisen ,  James A. Kahle ,  Hung Q. Le ,  Dung Q. Nguyen

发明人： Christopher M. Abernathy ,  Mary D. Brown ,  Susan E. Eisen ,  James A. Kahle ,  Hung Q. Le ,  Dung Q. Nguyen

IPC分类号： G06F12/02

CPC分类号： G06F9/30101 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/461

摘要： Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.

摘要翻译： 可以使用各种系统，过程，产品和技术来管理线程转换。 在特定实现中，用于管理线程转换的系统和过程可以包括确定要对两个数据寄存器组的相对使用进行转换的能力，并且基于转换确定来确定是否将线程数据移入 至少一个数据寄存器设置为二级寄存器。 系统和过程还可以包括基于移动确定将线程数据从至少一个数据寄存器集合移动到第二级寄存器的能力。

公开(公告)号：US08386753B2

公开(公告)日：2013-02-26

申请号：US12423561

申请日：2009-04-14

申请人： Susan E. Eisen ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

发明人： Susan E. Eisen ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

IPC分类号： G06F9/38

CPC分类号： G06F9/485

摘要： A mechanism is provided for thread completion arbitration. The mechanism comprises executing more than two threads of instructions simultaneously in the processor, selecting a first thread from a first subset of threads, in the more than two threads, for completion of execution within the processor, and selecting a second thread from a second subset of threads, in the more than two threads, for completion of execution within the processor. The mechanism further comprises completing execution of the first and second threads by committing results of the execution of the first and second threads to a storage device associated with the processor. At least one of the first subset of threads or the second subset of threads comprise two or more threads from the more than two threads. The first subset of threads and second subset of threads have different threads from one another.

摘要翻译： 提供线程完成仲裁的机制。 该机制包括在处理器中同时执行多于两个指令的线程，在多于两个线程中从线程的第一子集中选择第一线程，以完成处理器内的执行，以及从第二子集中选择第二线程 的线程，在两个以上的线程中，用于完成处理器内的执行。 该机制还包括通过将执行第一和第二线程的结果提交到与处理器相关联的存储设备来完成第一和第二线程的执行。 线程的第一子集或线程的第二子集中的至少一个包括来自多于两个线程的两个或多个线程。 线程的第一个子集和线程的第二个子集具有彼此不同的线程。

公开(公告)号：US20080263331A1

公开(公告)日：2008-10-23

申请号：US11736855

申请日：2007-04-18

申请人： Hung Q. Le ,  Dung Q. Nguyen ,  Balaram Sinharoy

发明人： Hung Q. Le ,  Dung Q. Nguyen ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/384

摘要： A universal register rename mechanism for instructions with multiple targets using a common destination tag. For each instruction that updates multiple destinations, a single rename entry is allocated to handle all destinations associated with it. A rename entry now consists of a DTAG and a vector to indicate the type of destination(s) that is/are being updated by such a particular instruction. For example, a common DTAG can be assigned to a fixed point unit instruction (FXU) that updates general purpose register (GPR), fixed point exception register (XER), and condition code register (CR) destinations. During flush time, the DTAGs in the recovery link may be used to restore the information indicating that the youngest instruction updates a particular architected register. By using a single, universal rename structure for all types of destinations, a large saving in silicon and power can be realized without the need to sacrifice performance.

摘要翻译： 通用寄存器重命名机制，用于使用公共目标标签的多个目标的指令。 对于更新多个目的地的每个指令，分配单个重命名条目来处理与其相关联的所有目的地。 现在，一个重命名条目由一个DTAG和一个向量组成，用于指示由这样的特定指令更新的目标的类型。 例如，可以将普通DTAG分配给更新通用寄存器（GPR），定点异常寄存器（XER）和条件码寄存器（CR）目的地的固定点单元指令（FXU）。 在冲洗时间期间，恢复链路中的DTAG可以用于恢复指示最年轻的指令更新特定架构的寄存器的信息。 通过为所有类型的目的地使用单一的通用重命名结构，可以实现大量的硅和电源节省，而不需要牺牲性能。

公开(公告)号：US20080263321A1

公开(公告)日：2008-10-23

申请号：US11736844

申请日：2007-04-18

申请人： Hung Q. Le ,  Dung Q. Nguyen ,  Balaram Sinharoy

发明人： Hung Q. Le ,  Dung Q. Nguyen ,  Balaram Sinharoy

IPC分类号： G06F15/00

CPC分类号： G06F9/384 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3861

摘要： A unified register rename mechanism for targets of different instruction types is provided in a microprocessor. The universal rename mechanism renames destinations of different instruction types using a single rename structure. Thus, an instruction that is updating a floating point register (FPR) can be renamed along with an instruction that is updating a general purpose register (GPR) or vector multimedia extensions (VMX) instructions register (VR) using the same rename structure because the number of architected states for GPR is the same as the number of architected states for FPR and VR. Each destination tag (DTAG) is assigned to one destination. A floating point instruction may be assigned to a DTAG, and then a fixed point instruction may be assigned to the next DTAG and so forth. With a universal rename mechanism, significant silicon and power can be saved by having only one rename structure for all instruction types.

摘要翻译： 在微处理器中提供了用于不同指令类型的目标的统一寄存器重命名机制。 通用重命名机制使用单个重命名结构重命名不同指令​​类型的目标。 因此，更新浮点寄存器（FPR）的指令可以与使用相同的重命名结构更新通用寄存器（GPR）或向量多媒体扩展（VMX）指令寄存器（VR））的指令一起重命名，因为 GPR的架构状态数量与FPR和VR的架构状态数量相同。 每个目的地标签（DTAG）被分配到一个目的地。 可将浮点指令分配给DTAG，然后将固定点指令分配给下一个DTAG等等。 使用通用重命名机制，可以通过为所有指令类型只有一个重命名结构来节省显着的硅和功率。

公开(公告)号：US20080072018A1

公开(公告)日：2008-03-20

申请号：US11533379

申请日：2006-09-20

申请人： Hung Q. Le ,  Dung Q. Nguyen

发明人： Hung Q. Le ,  Dung Q. Nguyen

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855

摘要： A method of data processing includes fetching a sequence of instructions, assigning each instruction within the sequence a respective unique instruction tag, and associating a respective destination vector with each instruction. The destination vectors, which are of uniform size, identify which of a plurality of possible destinations for execution results are targeted by the associated instructions. Data dependency between instructions in the sequence is managed by reference to the destination vectors associated with the instructions.

摘要翻译： 一种数据处理方法包括获取一系列指令，在序列内分配相应唯一指令标签中的每条指令，并将各目标向量与每条指令相关联。 具有相同大小的目的地向量识别用于执行结果的多个可能目的地中的哪一个被相关联的指令所针对。 通过参考与指令相关联的目的地向量来管理序列中的指令之间的数据相关性。

公开(公告)号：US08661228B2

公开(公告)日：2014-02-25

申请号：US13448024

申请日：2012-04-16

申请人： Christopher M. Abernathy ,  Mary D. Brown ,  Hung Q. Le ,  Dung Q. Nguyen

发明人： Christopher M. Abernathy ,  Mary D. Brown ,  Hung Q. Le ,  Dung Q. Nguyen

IPC分类号： G06F9/34

CPC分类号： G06F9/3851 ,  G06F9/30138

摘要： A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a first level register file having lower access latency and a second level register file having higher access latency. Each of the first and second level register files includes a plurality of physical registers for holding operands that is concurrently shared by a plurality of threads. The processor further includes a mapper that, at dispatch of an instruction specifying a source logical register from the instruction fetch unit to the issue queue, initiates a swap of a first operand associated with the source logical register that is in the second level register file with a second operand held in the first level register file. The issue queue, following the swap, issues the instruction to the execution unit for execution.