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    Multiple chip package processor having feed through paths on one die
    1.
    发明授权
    Multiple chip package processor having feed through paths on one die 失效
    多芯片封装处理器具有一个管芯上的馈通通路

    公开(公告)号：US5606710A

    公开(公告)日：1997-02-25

    申请号：US359417

    申请日：1994-12-20

    申请人： Christopher M. Hall ,  Gary D. Phillips ,  William E. Miller ,  David W. Weinrich ,  Robert M. Salter, III ,  Richard E. Crippen

    发明人： Christopher M. Hall ,  Gary D. Phillips ,  William E. Miller ,  David W. Weinrich ,  Robert M. Salter, III ,  Richard E. Crippen

    IPC分类号： G06F15/78 ,  G11C16/10 ,  G06F13/00

    CPC分类号： G11C16/102 ,  G06F15/7814 ,  Y02B60/1207 ,  Y02B60/1225

    摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. A plurality of feed-throughs are provided on the non-volatile memory die to provide communication paths from the processor die to package pads which are in the shadow of the non-volatile memory die relative to the processor die and thus prevent direct connection from the processor die to the package pad. In normal run mode, these pads are exclusively used as feed-through, providing a direct connection between a specific pad on the processor die and a specific pad on the package. In other modes of operation, however, the signals input from (or output to) the feed-through package pads are re-routed by transfer gates to the non-volatile memory die.

    摘要翻译： 一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。 该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能 的操作和其他控制信号。 在非易失性存储器管芯上提供多个馈通以提供从处理器管芯到非易失性存储器管芯相对于处理器管芯的阴影中的封装焊盘的通信路径，从而防止从 处理器裸片到封装垫。 在正常运行模式下，这些焊盘专门用作馈通，提供处理器管芯上的特定焊盘与封装上的特定焊盘之间的直接连接。 然而，在其他操作模式中，从（或输出到）馈通封装焊盘输入的信号通过传输门被重新路由到非易失性存储器管芯。

    In-system programming architecture for a multiple chip processor
    2.
    发明授权
    In-system programming architecture for a multiple chip processor 失效
    用于多芯片处理器的系统内编程架构

    公开(公告)号：US5566344A

    公开(公告)日：1996-10-15

    申请号：US445006

    申请日：1995-05-19

    申请人： Christopher M. Hall ,  Gary D. Phillips ,  William E. Miller ,  David W. Weinrich ,  Richard E. Crippen ,  Robert M. Salter, III

    发明人： Christopher M. Hall ,  Gary D. Phillips ,  William E. Miller ,  David W. Weinrich ,  Richard E. Crippen ,  Robert M. Salter, III

    IPC分类号： G06F15/78 ,  G11C16/10 ,  G06F15/76

    CPC分类号： G11C16/102 ,  G06F15/7814 ,  Y02B60/1207 ,  Y02B60/1225

    摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.The processor can be programmed internally or externally. In the in-system programming mode, the processor program counter is used to fetch running instructions out of an on-board ROM instruction memory on the processor die. The processor core outputs an address into which data is to be programmed on its output data bus. The processor core then receives from an external device the data which is to be programmed into the selected address and outputs it serially onto the data bus and therefrom to the memory die. The address and program data are then parallel output from separate registers on the memory die along with a program pulse to program the memory core.

    摘要翻译： 一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。 该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能 的操作和其他控制信号。 处理器可以在内部或外部进行编程。 在系统内编程模式下，处理器程序计数器用于从处理器管芯上的板载ROM指令存储器中获取运行指令。 处理器内核在其输出数据总线上输出要编程数据的地址。 然后，处理器核心从外部设备接收要被编程到所选择的地址中的数据，并将其串行地输出到数据总线上并从其输出到存储器管芯。 然后，地址和程序数据与存储器管芯上的单独寄存器一起并行输出，并且与编程脉冲一起编程存储器内核。

    Multiple chip processor architecture with reset intercept circuit
    3.
    发明授权
    Multiple chip processor architecture with reset intercept circuit 失效
    具有复位截止电路的多芯片处理器架构

    公开(公告)号：US5598573A

    公开(公告)日：1997-01-28

    申请号：US446018

    申请日：1995-05-19

    申请人： Christopher M. Hall ,  Gary D. Phillips ,  David W. Weinrich ,  Robert M. Salter, III

    发明人： Christopher M. Hall ,  Gary D. Phillips ,  David W. Weinrich ,  Robert M. Salter, III

    IPC分类号： G06F15/78 ,  G11C16/10 ,  G06F15/76

    CPC分类号： G11C16/102 ,  G06F15/7814 ,  Y02B60/1207 ,  Y02B60/1225

    摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. A reset intercept circuit is provided on the non-volatile memory die for intercepting the signal which is provided to the reset input of the non-volatile memory die from external of the multi chip package. The reset intercept circuit provides a modified version thereof to the processor die. Particularly, the reset intercept circuit performs the function of sending a modified version of the reset signal to the processor die responsive to the present mode of operation of the multi chip package at the time the reset signal is received.

    摘要翻译： 一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。 该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能 的操作和其他控制信号。 复位截止电路设置在非易失性存储器管芯上，用于截取从多芯片封装的外部提供给非易失性存储器管芯的复位输入的信号。 复位截取电路将其修改版本提供给处理器管芯。 特别地，复位截取电路响应于接收到复位信号时的多芯片封装的当前工作模式，执行将复位信号的修改版本发送到处理器管芯的功能。

    Non-volatile memory control and data loading architecture for multiple chip processor
    4.
    发明授权
    Non-volatile memory control and data loading architecture for multiple chip processor 失效
    用于多芯片处理器的非易失性存储器控制和数据加载架构

    公开(公告)号：US5623686A

    公开(公告)日：1997-04-22

    申请号：US446079

    申请日：1995-05-19

    申请人： Christopher M. Hall ,  Gary D. Phillips ,  William E. Miller ,  David W. Weinrich ,  Robert M. Salter, III ,  Richard E. Crippen

    发明人： Christopher M. Hall ,  Gary D. Phillips ,  William E. Miller ,  David W. Weinrich ,  Robert M. Salter, III ,  Richard E. Crippen

    IPC分类号： G06F15/78 ,  G11C16/10 ,  G06F15/76

    CPC分类号： G11C16/102 ,  G06F15/7814 ,  Y02B60/1207 ,  Y02B60/1225

    摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.An input data register on the non-volatile memory die and a related multiplexer allows data from different sources to be loaded into the input data register depending on the mode of operation. Also, the output of the input data register is coupled to plural locations so that the destination of the data can also be switched responsive to the mode of operation. Particularly, the output of the input data register is coupled to an output port, a program data register (through which program data can be loaded into the program memory), and a control register for setting various control bits for performing specific integrity tests which can be performed following fabrication. Accordingly, the input data register is used for programming the memory from an external source, setting control bits from an external device, and sending data from the processor to the R port and on to external devices.

    摘要翻译： 一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。 该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能 的操作和其他控制信号。 非易失性存储器管芯上的输入数据寄存器和相关的多路复用器允许根据操作模式将来自不同源的数据加载到输入数据寄存器中。 此外，输入数据寄存器的输出耦合到多个位置，使得数据的目的地也可以响应于操作模式而被切换。 特别地，输入数据寄存器的输出耦合到输出端口，程序数据寄存器（程序数据可以通过其加载到程序存储器中）和控制寄存器，用于设置用于执行特定完整性测试的各种控制位， 在制造之后执行。 因此，输入数据寄存器用于从外部源编程存储器，从外部设备设置控制位，并将数据从处理器发送到R端口并传输到外部设备。

    Multiple chip processor architecture with memory interface control register for in-system programming
    5.
    发明授权
    Multiple chip processor architecture with memory interface control register for in-system programming 失效
    具有存储器接口控制寄存器的多芯片处理器架构，用于在系统编程

    公开(公告)号：US5581779A

    公开(公告)日：1996-12-03

    申请号：US445007

    申请日：1995-05-19

    申请人： Christopher M. Hall ,  Gary D. Phillips ,  William E. Miller ,  David W. Weinrich ,  Robert M. Salter, III ,  Richard E. Crippen

    发明人： Christopher M. Hall ,  Gary D. Phillips ,  William E. Miller ,  David W. Weinrich ,  Robert M. Salter, III ,  Richard E. Crippen

    IPC分类号： G06F15/78 ,  G11C16/10 ,  G06F15/76

    CPC分类号： G11C16/102 ,  G06F15/7814 ,  Y02B60/1207 ,  Y02B60/1225

    摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.The processor includes an in-system programming mode including first and second memory interface control registers on the processor die and the memory die, respectively, for receiving control bits from the processor core for controlling multiplexers on the dies. The various bit output lines of the first memory interface control register are coupled to the control inputs of the multiplexers.

    摘要翻译： 一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。 该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能 的操作和其他控制信号。 处理器包括分别包括处理器管芯和存储管芯上的第一和第二存储器接口控制寄存器的系统内编程模式，用于从处理器核心接收控制位以控制管芯上的多路复用器。 第一存储器接口控制寄存器的各个位输出线耦合到多路复用器的控制输入端。

    Serial register multi-input multiplexing architecture for multiple chip processor
    6.
    发明授权
    Serial register multi-input multiplexing architecture for multiple chip processor 失效
    串行寄存器多输入复用架构，适用于多芯片处理器

    公开(公告)号：US5613144A

    公开(公告)日：1997-03-18

    申请号：US444532

    申请日：1995-05-19

    申请人： Christopher M. Hall ,  Gary D. Phillips ,  David W. Weinrich

    发明人： Christopher M. Hall ,  Gary D. Phillips ,  David W. Weinrich

    IPC分类号： G06F15/78 ,  G11C16/10 ,  G06F15/76

    CPC分类号： G11C16/102 ,  G06F15/7814 ,  Y02B60/1207 ,  Y02B60/1225

    摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.

    摘要翻译： 一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。 该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能 的操作和其他控制信号。

    EPROM register providing a full time static output signal
    7.
    发明授权
    EPROM register providing a full time static output signal 失效
    EPROM寄存器提供全时静态输出信号

    公开(公告)号：US5274778A

    公开(公告)日：1993-12-28

    申请号：US532065

    申请日：1990-06-01

    申请人： Christopher M. Hall

    发明人： Christopher M. Hall

    IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/115 ,  G06F12/00 ,  G11C29/00

    CPC分类号： G11C16/26 ,  G11C16/10

    摘要： An EPROM register is programmed in a manner substantially similar to the manner used to program a main EPROM array contained on the same integrated circuit. Data in the main EPROM array must be read out by applying appropriate address and output enable signals. The EPROM register allows the data stored therein to be available at all times by providing a full-time static output signal. The register includes a static evaluation circuit for determining the data stored in the register, a precharge keeper circuit for providing a pseudo-static evaluation of the data, as well as providing a periodic refresh of the sense node during pseudo-static evaluation, and a margin test circuit for testing the threshold voltage of the register, as well as actual or relative shifts in the threshold voltage. The EPROM register serves as a nonvolatile memory which can be written to store configuration information for an integrated circuit.

    Modular gray code counter
    9.
    发明授权
    Modular gray code counter 失效
    模块灰色代码计数器

    公开(公告)号：US5097491A

    公开(公告)日：1992-03-17

    申请号：US531004

    申请日：1990-05-31

    申请人： Christopher M. Hall

    发明人： Christopher M. Hall

    IPC分类号： H03K21/00 ,  H03K21/40 ,  H03K23/00

    CPC分类号： H03K23/005

    摘要： A Gray Code counter is provided having synchronous, modular circuits for each of the three types of bit positions, i.e., least significant bit ("LSB"), most significant bit ("MSB") and middle bit ("MB"). One LSB and MSB circuit each are used with as many MB circuits in between as are necessary to provide a counter having the desired number of bits. The LSB, MSB and MB circuits' designs are truly modular in that duplicate MB circuits can be freely coupled together between an LSB circuit and an MSB circuit to provide the desired number of counter bits without modifying any input or output interfaces between the circuits. The counter can count either up or down in accordance with a normal Gray Code sequence.